DS92LV2421 Datasheet, PDF (14/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

Symbol
Parameter
Conditions
t_XZR
Active to OFF Delay, Figure 12 OSS_SEL = 0
t_DDLT
t_DD
t_DPJ
Deserializer Lock Time,
Figure 13
SSC[3:0] = OFF,
(Note 6)
SSC[3:0] = ON,
(Note 6)
Des Delay - Latency, Figure 11
Des Period Jitter
SSC[3:0] = OFF,
(Note 8)
t_DCCJ Des Cycle-to-Cycle Jitter
SSC[3:0] = OFF,
(Note 9)
t_RJIT
Des Input Jitter Tolerance,
Figure 16
BIST Mode
t_PASS
BIST PASS Valid Time,
BISTEN = 1, Figure 17
SSCG Mode
f_DEV
Spread Spectrum
Clocking Deviation
Frequency
f_MOD
Spread Spectrum
Clocking Modulation
Frequency
EQ = OFF
Pin/Freq.
DO[23:0], CO1, CO2,
CO3, LOCK, PASS,
CLKOUT
CLKOUT = 10 to 75
MHz
CLKOUT = 10 to 75
MHz
CLKOUT = 10 to 75
MHz
CLKOUT = 10 to 75
MHz
CLKOUT = 10 to 75
MHz
CLKOUT = 10 to 75
MHz
CLKOUT = 10 to 65
MHz,
SSC[3:0] = ON
CLKOUT = 10 to 65
MHz,
SSC[3:0] = ON
Recommended Timing for the Serial Control Bus
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
f_SCL
SCL Clock Frequency
Standard Mode
Fast Mode
t_LOW
SCL Low Period
Standard Mode
Fast Mode
t_HIGH SCL High Period
Standard Mode
Fast Mode
t_HD;STA
Hold time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
t_SU:STA
Set Up time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
t_HD;DAT Data Hold Time,
Figure 18
Standard Mode
Fast Mode
t_SU;DAT Data Set Up Time,
Figure 18
Standard Mode
Fast Mode
t_SU;STO Set Up Time for STOP
Condition, Figure 18
Standard Mode
Fast Mode
Min Typ Max Units
TBD ns
10
ms
10
ms
140*T TBD ns
TBD
UI
±1
ns
TBD
UI
±300 ps
0.5 TBD UI
TBD
10
ns
±0.5
±2
%
8
100 kHz
Min Typ Max Units
100 kHz
400 kHz
4.7
us
1.3
us
4.0
us
0.6
us
4.0
us
0.6
us
4.7
us
0.6
us
0
3.45
us
0
0.9
us
250
ns
100
ns
4.0
us
0.6
us
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