PC87417 Datasheet, PDF (222/257 Pages) National Semiconductor (TI) – LPC ServerI/O for Servers and Workstations

10.0 Legacy Functional Blocks (Continued)
10.2 PARALLEL PORT
10.2.1 General Description
The Parallel Port supports all IEEE1284 standard communication modes:
q _{Compatibility (known also as Standard or SPP).}
q _{Bidirectional (known also as PS/2).}
q _FIFO.
q _{EPP (known also as Mode 4).}
q _{ECP (with an optional Extended ECP mode).}
10.2.2 Parallel Port Register Map
The Parallel Port includes two groups of runtime registers, as follows:
• A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h)
are used only in the Extended ECP mode.
• A group of four registers, used only in the Extended ECP mode, accessed by a second level offset.
EPP and second level offset registers are available only when the base address is 8-byte aligned.
The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-
isters are used and which address bits are used for the base address. See Tables 60 and 61 for a listing of all registers, their
offset addresses and the associated modes. All registers are V_DD powered.
Table 60. Parallel Port Registers at First Level Offset
Offset
Mnemonic
Mode(s)
Register Name
Type
00h
DATAR
0,1
Data
R/W
AFIFO
3
ECP FIFO (Address)
W
DTR
4
Data (for EPP)
R/W
01h
DSR
0,1,2,3 Status
RO
STR
4
Status (for EPP)
RO
02h
DCR
0,1,2,3 Control
R/W
CTR
4
Control (for EPP)
R/W
03h
ADDR
4
EPP Address
R/W
04h
DATA0
4
EPP Data Port 0
R/W
05h
DATA1
4
EPP Data Port 1
R/W
06h
DATA2
4
EPP Data Port 2
R/W
07h
DATA3
4
EPP Data Port 3
R/W
400h
CFIFO
2
PP Data FIFO
W
DFIFO
3
ECP Data FIFO
R/W
TFIFO
6
Test FIFO
R/W
CNFGA
7
Configuration A
RO
401h
CNFGB
7
Configuration B
RO
402h
ECR
0,1,2,3 Extended Control
R/W
403h
EIR¹
0,1,2,3 Extended Index
R/W
404h
EDR¹
0,1,2,3 Extended Data
R/W
405h
EAR¹
0,1,2,3 Extended Auxiliary Status ^R/W
1. These registers are extended to the standard IEEE1284 registers. They
are only accessible when enabled by bit 4 of the Parallel Port Configuration
register (see Section 3.9.3 on page 62).
www.national.com
222
Revision 1.2