PC87417 Datasheet, PDF (195/257 Pages) National Semiconductor (TI) – LPC ServerI/O for Servers and Workstations

9.0 System Wake-Up Control (SWC) (Continued)
9.3.18 Keyboard Data Shift Register (KDSR)
When keyboard wake-up detection is enabled, this register stores the keyboard data shifted in from the keyboard during
transmission. It is reset by hardware to 00h.
Power Well:V_PP
Location: Bank 0, Offset 16h
Type: RO
Bit
Name
Reset
7
6
5
4
3
2
1
0
Keyboard Data
0
0
0
0
0
0
0
0
Bit
7-0 Keyboard Data.
Description
9.3.19 Mouse Data Shift Register (MDSR)
When mouse wake-up detection is enabled, this register stores the mouse data shifted in from the mouse during
transmission. It is reset by hardware to 00h.
Power Well:V_PP
Location: Bank 0, Offset 17h
Type: RO
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
Mouse Data
0
0
0
0
0
0
0
0
Bit
7-3 Reserved.
2-0 Mouse Data.
Description
9.3.20 PS2 Keyboard Key Data 0 to 7 Registers (PS2KEY0 to PS2KEY7)
These eight registers (PS2KEY0-PS2KEY7) store the data bytes for Special Key Sequence or Password mode
(KBDMODE = 0) or for Power Management Key mode (KBDMODE = 1) of the Keyboard/Mouse Wake-up Detector.
In Special Key Sequence or in Password modes, the keyboard data is stored as follows:
q _{PS2KEY0 register stores the data byte for the first key in the sequence.}
q _{PS2KEY1 register stores the data byte for the second key in the sequence.}
q _{PS2KEY2 - PS2KEY7 registers store data bytes for the third to eighth key in the sequence.}
For keyboard data storage in Power Management Key mode, see Section 9.3.16 on page 193.
When one of these registers is set to 00h, it indicates that the value of the corresponding data byte is ignored (not compared).
These registers are reset by hardware to 00h.
Power Well: V_PP
Location: Bank 0, Offset 18h to 1Fh
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Data Byte of Key
0
0
0
0
0
0
0
0
Bit
7-0 Data Byte of Key.
Description
Revision 1.2
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