LMH7324_0710 Datasheet, PDF (13/20 Pages) National Semiconductor (TI) – Quad 700 ps High Speed Comparator with RSPECL Outputs

FIGURE 7. ANALOG TO LVDS
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STANDARD COMPARATOR SETUP
Figure 8 shows a standard comparator setup which creates
RSPECL levels because the V_CCO supply voltage is +5V. In
this setup the V_EE pin is connected to the ground level. The
V_CCI pin is connected to the V_CCO pin because there is no
need to use different positive supply voltages. The input sig-
nal is AC coupled to the positive input. To maintain reliable
results, even for signals with larger amplitudes, the input pins
IN+ and IN− are biased at 1.4V through a resistive divider
using a resistor of 1 kΩ to ground and a resistor of 2.5 kΩ to
the V_CC and by adding two decoupling capacitors. Both inputs
are connected to the bias level by the use of a 10 kΩ resistor.
With this input configuration the input stage can work in a lin-
ear area with signals of approximately 3 V_PP. (See input level
restrictions in the data tables.)
DELAY AND DISPERSION
Comparators are widely used to connect the analog world to
the digital one. The accuracy of a comparator is dictated by
its DC properties, such as offset voltage and hysteresis, and
by its timing aspects, such as rise and fall times and delay.
For low frequency applications most comparators are much
faster than the analog input signals they handle. The timing
aspects are less important here than the accuracy of the input
switching levels. The higher the frequencies, the more impor-
tant the timing properties of the comparator become, because
the response of the comparator can make a noticeable
change in critical parameters such as time frame or duty cy-
cle. A designer has to know these effects and has to deal with
them. In order to predict what the output signal will do, several
parameters are defined which describe the behavior of the
comparator. For a good understanding of the timing parame-
ters discussed in the following section, a brief explanation is
given and several timing diagrams are shown for clarification.
PROPAGATION DELAY
The propagation delay parameter is described in the definition
section. Two delay parameters can be distinguished, t_PDH and
t_PDL as shown in Figure 9. Both parameters do not necessarily
have the same value. It is possible that differences will occur
due to a different response of the internal circuitry. As a
derivative of this effect another parameter is defined: Δt_PD.
This parameter is defined as the absolute value of the differ-
ence between t_PDH and t_PDL.
FIGURE 8. Standard Setup
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FIGURE 9. Propagation Delay
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