LMH7324_0710 Datasheet, PDF (12/20 Pages) National Semiconductor (TI) – Quad 700 ps High Speed Comparator with RSPECL Outputs

TIPS & TRICKS USING THE LMH7324
This section discusses several aspects concerning special
applications using the LMH7324.Topics include the connec-
tion of the DAP in conjunction to the V_EE pins and the use of
this part as an interface between several logic families. Other
sections discuss several widely used definitions and terms for
comparators. The final sections explain some aspects of
transmission lines and the choice for the most suitable com-
ponents handling very fast pulses.
THE DAP AND THE V_EE PINS
To protect the device against damage during handling and
production, two antiparallel connected diodes are placed be-
tween the V_EE pins. Under normal operating conditions (all
V_EE pins have the same voltage level) these diodes are not
functioning, as can be seen in Figure 4.
The DAP (Die Attach Paddle) functions as a heat sink which
means that heat can be transferred, using vias below this pad,
to any appropriate copper plane.
FIGURE 5. ECL TO RSPECL
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Interface from PECL to (RS) ECL
This setup needs the V_CCI pin at +5V because the input logic
levels are positive. To obtain the ECL levels at the output it is
necessary to connect the V_CCO to the ground while the V_EE
has to be connected to the −5.2V. The reason for this is that
the minimum requirement for the supply is 5V. The high level
of the output of the LMH7324 is normally 1.1V below the
V_CCO supply voltage, and the low level is 1.5V below this sup-
ply. The output levels are now −1100 mV for the logic ‘1’ and
−1500 mV for the logic ‘0’. (See Figure 6.)
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FIGURE 4. DAP and V_EE Configuration
INTERFACE BETWEEN LOGIC FAMILIES
The LMH7324 can be used to interface between different log-
ic families. The feature that facilitates this is the fact that the
input stage and the output stage use different positive power
supply pins which can be used at different voltages. The only
restriction is that the minimum supply voltage between V_EE
and one of the positive supplies must be 5V. The negative
supply pins are connected together for all four parts. Using
the power pins at different supply voltages makes it possible
to create several translations for logic families. It is possible
to translate from logic at negative voltage levels such as ECL
to logic at positive levels such as RSPECL and LVDS and vice
versa.
Interface from ECL to RSPECL
The supply pin V_CCI can be connected to ground because the
input levels are negative and V_EE is at −5.2V. With this setup
the minimum requirements for the supply voltage of 5V are
obtained. The V_CCO pin must operate at +5V to create the
RSPECL levels. (See Figure 5.)
FIGURE 6. PECL TO RSECL
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Interface from Analog to LVDS
As seen in Figure 7, the LMH7324 can be configured to create
LVDS levels. This is done by connecting the V_CCO to 2.5V. As
discussed before, the output levels are now at V_CCO −1.1V for
the logic ‘1’ and at V_CCO -1.5V for the logic ‘0’. These levels
of 1000 mV and 1400 mV comply with the LVDS levels. As
can be seen in this setup, an AC coupled signal via a trans-
mission line is used. This signal is terminated with 50Ω to the
ground. The input stage has its supply from +5V to −5V, which
means that the input common mode level is midway between
the input stage supply voltages.
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