IRF840 Datasheet, PDF (6/7 Pages) Motorola, Inc – N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR

SEMICONDUCTOR
IRF840 Series RRooHHSS
Nell High Power Products
Fig.12c. Maximum avalanche energy vs.
Drain current
1200
1000
800
TOP
BOTTOM
l_D
3.6A
5.1A
8.0A
600
400
200
V_DD = 50V
0
25
50
75
100
125
150
Junction temperature, T_J (°C)
Fig.13a. Basic gate charge waveform
V_GS
10V
Q_GS
Q_G
Q_GD
Charge
Fig.13b. Gate charge test circuit
Current Regulator
Same Type as D.U.T.
50KΩ
12V
0.2µF
0.3µF
V_GS
3mA
D.U.T.
+
V_DS
-
R_G
R_D
Current Sampling Resistors
Fig.14 Peak diode recovery dv/dt test circuit for N-Channel MOSFET
D.U.T.
+ Circuit Layout Considerations
• Low Stray lnductance
• Ground Plane
• Low Leakage lnductance
Current Transformer
-
+
-
+
-
R_G
• dv/dt controlled by RG
• Driver same type as D.U.T.
+
• l_SD controlled by Duty Factor "D"
V_DD
-
• D.U.T. -Device Under Test
Driver Gate Drive
P.W.
Period
P.W.
D=
Period
* V_GS=10V
D.U.T. I _SD Waveform
Reverse
Recovery
Body Diode Forward
Current
Current
di/dt
D.U.T. V_DS Waveform
Diode Recovery
dv/dt
V_DD
Re-Applied
Voltage
Body Diode
Inductor Curent
Forward Drop
Ripple ≤ 5%
I_SD
*VGS = 5V for Logic Level Devices
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