IRF840 Datasheet, PDF (4/7 Pages) Motorola, Inc – N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR

SEMICONDUCTOR
IRF840 Series RRooHHSS
Nell High Power Products
Fig.5 Typical capacitance vs. Drain-to-Source
voltage
2500
2000
VGS = 0V, f =1MHz
Ciss = C_gs +C_gd (C_ds = shorted )
Crss = Cgd
Coss = Cds +Cgd
1500
Ciss
1000
500
0
10⁰
Coss
Crss
10¹
Drain-to-Source voltage, V_DS (V)
Fig.6 Typical gate charge vs. Drain-to-Source
voltage
20
lD = 8A
16
12
VDS=400V
V_DS=250V
V_DS=100V
8
4
For test circuit
see figure 13
0
0
15
30
45
60
75
Total gate charge, Q_G (nC)
Fig.7 Typical Source-Drain diode forward
voltage
T_J = 15 0°C
10¹
T_J = 25 °C
VGS = 0V
10⁰
0.4
0.6
0.8
1.0
1.2
1.4
Source-to-Drain voltage, V_SD (V)
Fig.8 Maximum safe operating area
10²
10
Operation in This Area is Limited by R_DS(ON)
10µs
100µs
1
0.1
0.1
1ms
Note:
1. T_C = 25°C
2. TJ = 150°C
3. Single Pulse
10ms
1
10¹
10²
10³
10⁴
Drain-to-Source voltage, V_DS (V)
Fig.9 Maximum drain current vs.
Case temperature
8
6
4
2
www.nellsemi.com
0
25
50
75
100
125
150
Case temperature, T_C (°C)
Page 4 of 7