UPD30102 Datasheet, PDF (624/701 Pages) NEC – 64/32-bit Microprocessor

CHAPTER 27 CPU INSTRUCTION SET DETAILS
SB
31
26 25
SB
101000
6
base
5
21 20
Store Byte
16 15
rt
5
offset
16
SB
0
Format:
SB rt, offset (base)
Description:
The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address.
The least-significant byte of register rt is stored at the effective address.
Operation:
32 T:
vAddr <- ((offset15)¹⁶ || offset15...0) + GPR [base]
(pAddr, uncached) <- AddressTranslation (vAddr, DATA)
pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian³))
byte <- vAddr2...0 xor BigEndianCPU³
data <- GPR [rt]63 – 8 * byte...0 || 0^{8 * byte}
StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)
64 T:
vAddr <- ((offset15)⁴⁸ || offset15...0) + GPR [base]
(pAddr, uncached) <- AddressTranslation (vAddr, DATA)
pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian³))
byte <- vAddr2...0 xor BigEndianCPU³
data <- GPR [rt]63 – 8 * byte...0 || 0^{8 * byte}
StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
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