UPD30102 Datasheet, PDF (561/701 Pages) NEC – 64/32-bit Microprocessor

CHAPTER 27 CPU INSTRUCTION SET DETAILS
DADD
Doubleword Add
DADD
31
26 25
21 20
16 15
11 10
65
0
SPECIAL
000000
rs
rt
rd
0
00000
DADD
101100
6
5
5
5
5
6
Format:
DADD rd, rs, rt
Description:
The contents of general register rs and the contents of general register rt are added to form the result. The result
is placed into general register rd.
An overflow exception occurs if the carries out of bits 62 and 63 differ (2’s complement overflow). The destination
register rd is not modified when an integer overflow exception occurs.
This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user
or supervisor mode causes a reserved instruction exception.
Operation:
64 T: GPR [rd] <- GPR [rs] + GPR [rt]
Exceptions:
Integer overflow exception
Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode)
561