UPD30102 Datasheet, PDF (610/701 Pages) NEC – 64/32-bit Microprocessor

LWR
CHAPTER 27 CPU INSTRUCTION SET DETAILS
Load Word Right
(Continued)
Given a word in a register and a word in memory, the operation of LWR is as follows:
LWR
Register
Memory
A
B
C
D
E
F
G
H
I
J
K
L
MN
O
P
vAddr_2..0
BigEndianCPU = 0
destination
type offset
(LEM)
0
S SS SMNOP 3
0
1
S SS S EMNO 2
1
2
S SS S E FMN 1
2
3
S S S S E F GM 0
3
4
SSSS I JKL 3
4
5
SSSSE I JK 2
5
6
SSSSEF I J 1
6
7
SSSSEFG I 0
7
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
LEM
Type
Offset
S
Little-endian memory (BigEndianMem = 0)
AccessType (see Table 3-2) sent to memory
pAddr_2...0 sent to memory
sign-extend of destination
31
LWR
610