UPD30102 Datasheet, PDF (475/701 Pages) NEC – 64/32-bit Microprocessor

CHAPTER 24 SIU (SERIAL INTERFACE UNIT)
Bit4:
Break interrupt
The value of bit 4 becomes 1 when the spacing mode (logical 0) is held longer than the time required for
transmission of one word of receive data input (start bit + data bits + parity bit + stop bit).
This bit value returns “0” when the CPU reads the contents of the line status register.
When in FIFO mode, if a break interrupt is detected for one character in the FIFO, the character is
regarded as an error character and the CPU is notified of a break interrupt when that character reaches
the highest position in the FIFO.
When a break occurs, one “zero” character is sent to the FIFO. The RxD enters marking mode, and
when the next valid start bit is received, the next character can be transmitted.
Bit3:
Framing error
This indicates that the received character data did not include a correct stop bit.
The value of this becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or
parity bit. This bit value returns to 0 when the CPU reads the contents of the line status register.
When in FIFO mode, if a framing error is detected for one character in the FIFO, the character is
regarded as an error character and the CPU is notified of a framing error when that character reaches the
highest position in the FIFO.
When a framing error occurs, the SIU prepares for further synchronization. The next start bit is assumed
to be the cause of the framing error and further data is not accepted until the next start bit has been
sampled twice.
Bit2:
Parity error
This error indicates that the received character data does not satisfy the even-parity or odd-parity setting
specified by the even parity select bit.
The value of this becomes 1 when a parity error is detected. This bit value returns to 0 when the CPU
reads the contents of the line status register.
When in FIFO mode, if a parity error is detected for one character within the FIFO, the character is
regarded as an error character and the CPU is notified of a parity error when that character reaches the
highest position in the FIFO.
Bit1:
Overrun error (OE)
When the CPU transfers the next character to the receive buffer register before it reads the receive buffer
register, the characters existing in that register are deleted.
The value of this bit becomes 1 when overrun status is detected and returns to “0” when the CPU reads
the contents of the line status register.
When in FIFO mode, if the data exceeds the trigger level as it continues to be transferred to the FIFO,
even after the FIFO becomes full an overrun error will not occur until all characters are stored in the shift
register.
The CPU is notified as soon as an overrun error occurs. The characters in the shift register are
overwritten and are not transferred to the FIFO.
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