UPD780204 Datasheet, PDF (61/418 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 3 CPU ARCHITECTURE
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0,
acknowledgment of a vectored interrupt request specified as lower priority by the priority specification flag
registers (PR0L and PR0H) (refer to 16.3 (3) Priority specification flag registers (PR0L, PR0H)) is
disabled. Whether the interrupt request is actually acknowledged or not is controlled by the interrupt enable
flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction
execution.
(3) Stack pointer (SP)
This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-speed
RAM area (FB00H to FEFFH) can be set as the stack area.
Figure 3-13. Stack Pointer Format
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0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from
the stack memory.
Each stack operation saves/resets data as shown in Figures 3-14 and 3-15.
Caution Because RESET input makes SP contents undefined, be sure to initialize the SP before
instruction execution.
User’s Manual U11302EJ4V0UM
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