UPD780204 Datasheet, PDF (214/418 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 13 SERIAL INTERFACE CHANNEL 0
(3) Serial bus interface control register (SBIC)
This register sets the serial bus interface operation and displays statuses.
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
Figure 13-4. Format of Serial Bus Interface Control Register (1/2)
Symbol _{<7> <6> <5> <4> <3> <2> <1> <0> Address After reset}
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H
00H
R/W
R/W^Note
R/W
RELT
Used for bus release signal output.
When RELT = 1, the SO latch is set to 1. After SO latch setting, RELT is automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for command signal output.
When CMDT = 1, the SO latch is cleared to 0. After SO latch clearance, CMDT is automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R RELD Bus release detection
Clear conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
• When RESET input is applied
Set conditions (RELD = 1)
• When bus release signal (REL) is detected
R CMDD Command detection
Clear conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
Set conditions (CMDD = 1)
• When command signal (CMD) is detected
R/W
ACKT
The acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after
execution of the instruction to be set to 1, and after acknowledge signal output, ACKT is
automatically cleared to 0.
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
Note Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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User’s Manual U11302EJ4V0UM