UPD780204 Datasheet, PDF (392/418 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 20 INSTRUCTION SET
Instruc- Mnemonic
tion
Group
Operands
Call CALL
return
!addr16
CALLF !addr11
CALLT [addr5]
BRK
RET
RETI
RETB
Stack PUSH
manipu-
lation
POP
PSW
rp
PSW
rp
MOVW
Uncondi- _BR
tional
branch
Condi-
tional
branch
BC
BNC
BZ
BNZ
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Bytes
Clocks
Operation
Flag
Note 1 Note 2
Z AC CY
3
7
2
5
1
6
1
6
1
6
1
6
1
6
1
2
1
4
1
2
1
4
4
–
2
–
2
–
3
6
2
6
2
8
2
6
2
6
2
6
2
6
–
(SP–1) ← (PC+3)H, (SP–2) ← (PC+3)L,
PC ← addr16, SP ← SP–2
–
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L,
PC15–11 ← 00001, PC10–0 ← addr11,
SP ← SP–2
–
(SP–1) ← (PC+1)H, (SP–2) ← (PC+1)L,
PCH ← (00000000, addr5+1),
PCL ← (00000000, addr5),
SP ← SP–2
–
(SP–1) ← PSW, (SP–2) ← (PC+1)H,
(SP–3) ← (PC+1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP–3, IE ← 0
–
PCH ← (SP+1), PCL ← (SP),
SP ← SP+2
–
PCH ← (SP+1), PCL ← (SP),
R RR
PSW ← (SP+2), SP ← SP+3,
NMIS ← 0
–
PCH ← (SP+1), PCL ← (SP),
R RR
PSW ← (SP+2), SP ← SP+3
–
(SP–1) ← PSW, SP ← SP–1
–
(SP–1) ← rpH, (SP–2) ← rpL,
SP ← SP–2
–
PSW ← (SP), SP ← SP+1
R RR
–
rpH ← (SP+1), rpL ← (SP),
SP ← SP+2
10 SP ← word
8
SP ← AX
8
AX ← SP
–
PC ← addr16
–
PC ← PC + 2 + jdisp8
–
PCH ← A, PCL ← X
–
PC ← PC + 2 + jdisp8 if CY = 1
–
PC ← PC + 2 + jdisp8 if CY = 0
–
PC ← PC + 2 + jdisp8 if Z = 1
–
PC ← PC + 2 + jdisp8 if Z = 0
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC).
392
User’s Manual U11302EJ4V0UM