UPD780204 Datasheet, PDF (103/418 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 5 CLOCK GENERATOR
Figure 5-3. Format of Processor Clock Control Register
Symbol <7>
PCC MCC
<6>
FRC
<5>
CLS
<4>
CSS
3
2
1
0
0 PCC2 PCC1 PCC0
Address
FFFBH
After reset
04H
R/W
R/W^{Note 1}
R/W
CSS PCC2 PCC1 PCC0 CPU clock (fCPU) selection
0
0
0
0 fX
0
0
1 fX/2
0
1
0
fX/2²
0
1
1
fX/2³
1
0
0
fX/2⁴
1
0
0
0 fXT/2
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
Setting prohibited
R
CLS CPU clock status
0 Main system clock
1 Subsystem clock
R/W
FRC Subsystem clock feedback resistor selection
0 Internal feedback resistor used
1 Internal feedback resistor not used^{Note 2}
R/W
MCC
0
1
Main system clock oscillation control^{Note 3}
Oscillation possible
Oscillation stopped
Notes 1. Bit 5 is a read-only bit.
2. This bit can be set to 1 only when the subsystem clock is not used.
3. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system
clock oscillation. The STOP instruction should not be used.
Cautions 1. Bit 3 must be set to 0.
2. Do not set MCC while an external clock is being input. This is because the X2 pin is pulled
up to VDD.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
User’s Manual U11302EJ4V0UM
103