UPD789304 Datasheet, PDF (35/64 Pages) NEC – 8-BIT SINGLE-CHIP MICROCONTROLLER

µPD789304, 789306, 789314, 789316
Mnemonic
Operand
SET1
CLR1
SET1
CLR1
NOT1
CALL
CALLT
saddr. bit
sfr. bit
A. bit
PSW. bit
[HL]. bit
saddr. bit
sfr. bit
A. bit
PSW. bit
[HL]. bit
CY
CY
CY
!addr16
[addr5]
RET
RETI
PUSH
POP
MOVW
BR
PSW
rp
PSW
rp
SP, AX
AX, SP
!addr16
$addr16
AX
Bytes Clocks
Operation
3
6
(saddr. bit) ← 1
3
6
sfr. bit ← 1
2
4
A. bit ← 1
3
6
PSW. bit ← 1
2
10 (HL). bit ← 1
3
6
(saddr. bit) ← 0
3
6
sfr. bit ← 0
2
4
A. bit ← 0
3
6
PSW. bit ← 0
2
10 (HL). bit ← 0
1
2
CY ← 1
1
2
CY ← 0
1
2
CY ← CY
3
6
(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
1
8
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
1
6
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
1
8
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
1
2
(SP – 1) ← PSW, SP ← SP – 1
1
4
(SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
1
4
PSW ← (SP), SP ← SP + 1
1
6
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
2
8
SP ← AX
2
6
AX ← SP
3
6
PC ← addr16
2
6
PC ← PC + 2 + jdisp8
1
6
PCH ← A, PCL ← X
Flags
Z AC CY
× ××
× ××
1
0
×
R RR
R RR
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control
register (PCC).
Data Sheet U14384EJ1V0DS
35