UPD789304 Datasheet, PDF (33/64 Pages) NEC – 8-BIT SINGLE-CHIP MICROCONTROLLER

µPD789304, 789306, 789314, 789316
Mnemonic
Operand
ADD
ADDC
SUB
SUBC
AND
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
Bytes Clocks
Operation
2
4
A, CY ← A + byte
3
6
(saddr), CY ← (saddr) + byte
2
4
A, CY ← A + r
2
4
A, CY ← A + (saddr)
3
8
A, CY ← A + (addr16)
1
6
A, CY ← A + (HL)
2
6
A, CY ← A + (HL + byte)
2
4
A, CY ← A + byte + CY
3
6
(saddr), CY ← (saddr) + byte + CY
2
4
A, CY ← A + r + CY
2
4
A, CY ← A + (saddr) + CY
3
8
A, CY ← A + (addr16) + CY
1
6
A, CY ← A + (HL) + CY
2
6
A, CY ← A + (HL + byte) + CY
2
4
A, CY ← A – byte
3
6
(saddr), CY ← (saddr) – byte
2
4
A, CY ← A – r
2
4
A, CY ← A – (saddr)
3
8
A, CY ← A – (addr16)
1
6
A, CY ← A – (HL)
2
6
A, CY ← A – (HL + byte)
2
4
A, CY ← A – byte – CY
3
6
(saddr), CY ← (saddr) – byte – CY
2
4
A, CY ← A – r – CY
2
4
A, CY ← A – (saddr) – CY
3
8
A, CY ← A – (addr16) – CY
1
6
A, CY ← A – (HL) – CY
2
6
A, CY ← A – (HL + byte) – CY
2
4
A ← A ∧ byte
3
6
(saddr) ← (saddr) ∧ byte
2
4
A←A∧r
2
4
A ← A ∧ (saddr)
3
8
A ← A ∧ (addr16)
1
6
A ← A ∧ (HL)
2
6
A ← A ∧ (HL + byte)
Flags
Z AC CY
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
× ××
×
×
×
×
×
×
×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control
register (PCC).
Data Sheet U14384EJ1V0DS
33