MC88LV915T Datasheet, PDF (9/11 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88LV915T
CLOCK
@f
SYSTEM
CLOCK
SOURCE
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
AT POINT OF USE
MC88LV915T
PLL
2f
CMMU
CPU
CMMU
CMMU
CMMU CMMU
MC88LV915T
PLL
2f
CMMU CMMU
CPU ^CMMU
CMMU CMMU
CPU
CARD
CPU
CARD
MC88LV915T
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @ 2f
AT POINT OF USE
Figure 4. Representation of a Potential Multi–Processing Application Utilizing the MC88LV915T
for Frequency Multiplication and Low Board–to–Board Skew
MC88LV915T System Level Testing Functionality
3–state functionality has been added to the 100MHz version of the MC88LV915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q
output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–down resistor
must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high impedance.
With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can
also be used for low frequency board testing.
Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It will
take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high.
TIMING SOLUTIONS
9
BR1333 — Rev 6
MOTOROLA