MC88LV915T Datasheet, PDF (7/11 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

LOW
CRYSTAL ^{25MHz INPUT}
OSCILLATOR
EXTERNAL
LOOP
FILTER
25MHz FEEDBACK SIGNAL
HIGH
100MHz SIGNAL
RST
Q5
Q4
FEEDBACK
REF_SEL
SYNC[0] MC88LV915T
ANALOG VCC
RC1
ANALOG GND
2X_Q
Q/2
Q3
Q2
MC88LV915T
1:2 Input to “Q” Output Frequency Relationship
50MHz
“Q”
CLOCK
OUTPUTS
In this application, the Q/2 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The “Q”
outputs (Q0–Q4, Q5) will always run at 2X the Q/2
frequency, and the 2X_Q output will run at 4X the
Q/2 frequency.
Allowable Input Frequency Range:
FQ_SEL Q0
HIGH
Q1 ^PLL_EN
HIGH
5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)
2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
Note: If the OE/RST input is active, a pull–up or pull–down re-
sistor isn’t necessary at the FEEDBACK pin so it won’t when
the fed back output goes into 3–state.
Figure 2a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back
50MHz FEEDBACK SIGNAL
HIGH
100MHz SIGNAL
LOW
CRYSTAL
50MHZ INPUT
OSCILLATOR
EXTERNAL
LOOP
FILTER
RST Q5
Q4
FEEDBACK
REF_SEL
SYNC[0] MC88LV915T
ANALOG VCC
RC1
ANALOG GND
2X_Q
Q/2
Q3
Q2
25MHz
SIGNAL
1:1 Input to “Q” Output Frequency Relationship
50MHz
“Q”
CLOCK
OUTPUTS
In this application, the Q4 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the “Q” outputs) will
equal the SYNC frequency. The Q/2 output will al-
ways run at 1/2 the “Q” frequency, and the 2X_Q
output will run at 2X the “Q” frequency.
FQ_SEL Q0
HIGH
Q1 PLL_EN
HIGH
Allowable Input Frequency Range:
10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)
5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW)
Figure 2b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back
100MHz FEEDBACK SIGNAL
HIGH
CRYSTAL
OSCILLATOR
LOW
100MHz INPUT
EXTERNAL
LOOP
FILTER
RST
Q5
Q4
FEEDBACK
REF_SEL
SYNC[0] ^MC88LV915T
ANALOG VCC
RC1
ANALOG GND
2X_Q
Q/2
Q3
Q2
25MHz
SIGNAL
FQ_SEL Q0
Q1 ^PLL_EN
2:1 Input to “Q” Output Frequency Relationship
50MHz
“Q”
CLOCK
OUTPUTS
In this application, the 2X_Q output is connected
to the FEEDBACK input. The internal PLL will line
up the positive edges of 2X_Q and SYNC, thus the
2X_Q frequency will equal the SYNC frequency.
The Q/2 output will always run at 1/4 the 2X_Q fre-
quency, and the “Q” outputs will run at 1/2 the
2X_Q frequency.
Allowable Input Frequency Range:
HIGH
HIGH
20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)
10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
Figure 2c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back
TIMING SOLUTIONS
7
BR1333 — Rev 6
MOTOROLA