MC88LV915T Datasheet, PDF (2/11 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88LV915T
Pinout: 28–Lead PLCC (Top View)
OE/RST VCC Q5 GND Q4 VCC 2X_Q
4 3 2 1 28 27 26
FEEDBACK 5
25 Q/2
REF_SEL 6
24 GND
SYNC[0] 7
23 Q3
VCC(AN) 8
RC1 9
22 VCC
21 Q2
GND(AN) 10
20 GND
SYNC[1] 11
19 LOCK
12 13 14 15 16 17 18
FREQ_SEL GND Q0 VCC Q1 GND PLL_EN
FN SUFFIX
PLASTIC PLCC
CASE 776–02
PIN SUMMARY
Pin Name Num
I/O
Function
SYNC[0]
1 Input Reference clock input
SYNC[1]
1 Input Reference clock input
REF_SEL
1 _Input Chooses reference between sync[0] & Sync[1]
FREQ_SEL 1 Input Doubles VCO Internal Frequency (low)
FEEDBACK 1 Input Feedback input to phase detector
RC1
1 _Input Input for external RC network
Q(0–4)
5 _Output Clock output (locked to sync)
Q5
1 _Output Inverse of clock output
2x_Q
1 _Output 2 x clock output (Q) frequency (synchronous)
Q/2
1 _Output Clock output(Q) frequency ÷ 2 (synchronous)
LOCK
1 _Output Indicates phase lock has been achieved (high when locked)
OE/RST
1 _Input Output Enable/Asynchronous reset (active low)
PLL_EN
1 _Input Disables phase–lock for low freq. testing
VCC,GND
11
Power and ground pins (note pins 8, 10 are
“analog” supply pins for internal PLL only)
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — Rev 6