MC88LV915T Datasheet, PDF (8/11 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88LV915T
10µF LOW
FREQ BYPASS
0.1µF HIGH
FREQ
BYPASS
BOARD VCC
47Ω
8 ANALOG VCC
1MΩ
330Ω
ANALOG LOOP FILTER/VCO
9 RC1
SECTION OF THE
MC88LV915T 28–PIN PLCC
0.1µF (LOOP
PACKAGE (NOT DRAWN TO
FILTER CAP)
SCALE)
10 ANALOG GND
47Ω
BOARD GND
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES
IS ALL THAT IS NECESSARY TO USE THE MC88LV915T IN A NORMAL
DIGITAL ENVIRONMENT.
Figure 3. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV915T
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 3 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
The purpose of the bypass filtering scheme shown in
Figure 3 is to give the 88LV915T additional protection
from the power supply and ground plane transients that
can occur in a high frequency, high speed digital system.
1a.All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1c.There are no special requirements set forth for the loop
filter resistors (1MΩ and 330Ω). The loop filter capacitor
(0.1µF) can be a ceramic chip capacitior, the same as a
standard bypass capacitor.
1b.The 47Ω resistors, the 10µF low frequency bypass
capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will minimize the
88LV915T’s sensitivity to voltage transients from the
system digital VCC supply and ground planes. This filter
will typically ensure that a 100mV step deviation on the
digital VCC supply will cause no more than a 100pS phase
deviation on the 88LV915T outputs. A 250mV step
deviation on VCC using the recommended filter values
should cause no more than a 250pS phase deviation; if a
25µF bypass capacitor is used (instead of 10µF) a 250mV
VCC step should cause no more than a 100pS phase
deviation.
If good bypass techniques are used on a board design
near components which may cause digital VCC and
ground noise, the above described VCC step deviations
should not occur at the 88LV915T’s digital VCC supply.
1d.The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1MΩ
resistor provides the correct amount of current injection
into the charge pump (2–3µA). For the TFN55, 70 or 100,
if the VCO is running below 40MHz, a 1.5MΩ reference
resistor should be used (instead of 1MΩ).
2. In addition to the bypass capacitors used in the analog
filter of Figure 3, there should be a 0.1µF bypass
capacitor between each of the other (digital) four VCC pins
and the board ground plane. This will reduce output
switching noise caused by the 88LV915T outputs, in
addition to reducing potential for noise in the ‘analog’
section of the chip. These bypass capacitors should also
be tied as close to the 88LV915T package as possible.
MOTOROLA
8
TIMING SOLUTIONS
BR1333 — Rev 6