MC88LV915T Datasheet, PDF (5/11 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88LV915T
FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)
Symbol
Parameter
Guaranteed Minimum
Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output
100
Fmax (‘Q’)
Maximum Operating Frequency,
50
Q0–Q3 Outputs
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition.
Unit
MHz
MHz
AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 3.3V ±0.3V, Load = 50Ω Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
tPULSE _WIDTH
(Q0–Q4, Q5, Q/2)
Rise/Fall Time, All Outputs
(Between 0.8 to 2.0V)
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2
0.5
2.0
ns Into a 50Ω Load
Terminated to VCC/2
0.5tCYCLE – 0.5 ¹ 0.5tCYCLE + 0.5 ¹ ns Into a 50Ω Load
Terminated to VCC/2
tPULSE _WIDTH
(2X_Q Output)
Output Pulse Width:
2X_Q @ 1.5V
40MHz
66MHz
80MHz
100MHz
0.5tCYCLE – 1.5
0.5tCYCLE – 1.0
0.5tCYCLE – 1.0
0.5tCYCLE – 1.0
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
ns Into a 50Ω Load
Terminated to VCC/2
tCYCLE
(2x_Q Output)
Cycle–to–Cycle Variation
2x_Q @ VCC/2
40MHz
66MHz
80MHz
100MHz
tCYCLE – 600ps
tCYCLE – 300ps
tCYCLE – 300ps
tCYCLE – 400ps
tCYCLE + 600ps
tCYCLE + 300ps
tCYCLE + 300ps
tCYCLE + 400ps
tPD²
(With 1MΩ from RC1 to An VCC)
ns
SYNC Feedback
SYNC Input to Feedback Delay 66MHz
–1.65
–1.05
(Measured at SYNC0 or 1 and 80MHz
–1.45
–0.85
FEEDBACK Input Pins)
100MHz
–1.25
–0.65
tSKEWr³
Output–to–Output Skew Between Out-
—
(Rising) See Note 4 puts Q0–Q4, Q/2 (Rising Edges Only)
tSKEWf³
(Falling)
Output–to–Output Skew Between Out-
—
puts Q0–Q4 (Falling Edges Only)
tSKEWall³
Output–to–Output Skew 2X_Q, Q/2,
—
Q0–Q4 Rising, Q5 Falling
tLOCK⁴
Time Required to Acquire Phase–Lock
1.0
From Time SYNC Input Signal is
Received
500
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
750
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
750
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
10
ms Also Time to LOCK
Indicator High
tPZL⁵
Output Enable Time OE/RST to 2X_Q,
3.0
Q0–Q4, Q5, and Q/2
14
ns Measured With the
PLL_EN Pin Low
tPHZ,tPLZ⁵
Output Disable Time OE/RST to 2X_Q,
3.0
Q0–Q4, Q5, and Q/2
14
ns Measured With the
PLL_EN Pin Low
1. TCYCLE in this spec is 1/Frequency at which the particular output is running.
2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is
with C1 = 0.01µF.
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
TIMING SOLUTIONS
5
BR1333 — Rev 6
MOTOROLA