HC05 Datasheet, PDF (76/232 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

5.3.6 MCAN acceptance mask register (CACM)
The acceptance mask register specifies which of the corresponding bits in the acceptance code
register are relevant for acceptance filtering.
Note:
This register can only be accessed when the reset request bit in the CCNTRL register
is set.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
5
MCAN acceptance mask (CACM) $0025 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Undefined
AM0 – AM7 — Acceptance mask bits
When a particular bit in this register is clear this indicates that the corresponding bit in the
acceptance code register must be the same as its identifier bit, before a match will be detected.
The message will be accepted if all such bits match. When a bit is set, it indicates that the state of
the corresponding bit in the acceptance code register will not affect whether or not the message
is accepted.
1 (set) – Ignore corresponding acceptance code register bit.
0 (clear) – Match corresponding acceptance code register and identifier bits.
5.3.7 MCAN bus timing register 0 (CBT0)
Note:
This register can only be accessed when the reset request bit in the CCNTRL register
is set.
MCAN bus timing 0 (CBT0)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0026 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Undefined
SJW1, SJW0 — Synchronization jump width bits
The synchronization jump width defines the maximum number of system clock (t_SCL) cycles by
which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 5-1).
MOTOROLA
5-14
MOTOROLA CAN MODULE (MCAN)
MC68HC05X16
Rev. 1