HC05 Datasheet, PDF (128/232 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

8.2
PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous
register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no
effect on the D/A converters’ 8-bit resolution (see Figure 8-3).
Bus
Timer
f_OSC
SM bit = 0
÷2
frequency (f_OP) _÷4
clock
SF bit = 1
x4096
PLM
clock
SM bit = 1
÷32
SF bit = 0
x256
Figure 8-3 PLM clock selection
8.3
PLM during STOP mode
On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is
8
exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by
power-on or external reset the registers values are forced to $00.
8.4
PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
MOTOROLA
8-4
PULSE LENGTH D/A CONVERTERS
MC68HC05X16
Rev. 1