HC05 Datasheet, PDF (225/232 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

R8 – receive data bit 8 7-11
T8 – transmit data bit 8 7-11
WAKE – wake-up mode select bit 7-11
SCCR2 – serial communications control register 2 7-14
ILIE – idle line interrupt enable 7-14
RE – receiver enable 7-15
RIE – receiver interrupt enable 7-14
RWU – receiver wake-up 7-15
SBK – send break 7-15
TCIE – transmit complete interrupt enable 7-14
TE – transmitter enable 7-14
TIE – transmit interrupt enable 7-14
SCDR – serial communications data register 7-10
SCI
baud rate selection 7-20
block diagram 7-2
data format 7-5
receiver wake-up 7-5
start bit detection 7-6
timing diagrams 7-12
SCLK 2-13
SCP1, SCP0 bits in BAUD 7-18
SCR2, SCR1, SCR0 bits in BAUD 7-19
SCSR – serial communications status register 7-16
FE – framing error flag 7-17
IDLE – idle line detected flag 7-16
NF – noise error flag 7-17
OR – overrun error flag 7-17
RDRF – receive data register full flag 7-16
TC – transmit complete flag 7-16
TDRE – transmit data register empty flag 7-16
SCT2, SCT1, SCT0 bits in BAUD 7-18
, SEC bit in OPTR 3-8 B-11
self-check mode 2-2
, SFA, SFB bits in Miscellaneous 3-11 8-3
single-chip mode 2-1
SJW1, SJW0 bits in CBT0 5-14
SLEEP 5-24
SLEEP bit in CCOM 5-8
SLOW 2-8
, , SM bit in Miscellaneous 2-10 3-12 8-3
software force compare 6-11
SP – stack pointer 11-2
SPD bit in CCNTRL 5-6
T
T8 bit in SCCR1 7-11
TBA bit in CSTAT 5-11
TBF – transmit buffer 5-4
TBI – transmit buffer identifier register 5-20
ID10-ID3 – identifier bits 5-20
TC bit in SCSR 7-16
TCAP1, TCAP2 2-12
TCIE bit in SCCR2 7-14
TCMP1, TCMP2 2-12
TCR – timer control register 6-4
FOLV2, FOLV1 – force output compare bits 6-5
ICIE – input capture interrupt enable 6-4
IEDG1 – input edge bit 6-5
OCIE – output compare interrupt enable 6-4
OLV2, OLV1 – output level bits 6-5
TOIE – timer overflow interrupt enable 6-4
TCS bit in CSTAT 5-11
TDO
SCI transmit data out 7-8
TDO – transmit data out 2-12
TDRE bit in SCSR 7-16
TDS – transmit data segment registers 5-21
DB7-DB0 – data bits 5-21
TE bit in SCCR2 7-14
TIE bit in CCNTRL 5-6
TIE bit in SCCR2 7-14
TIF bit in CINT 5-12
timing diagrams
ECLK 4-3
programmable timer 6-12
reset 10-1
SCI data clock 7-12
TOF bit in TSR 6-6
TOIE bit in TCR 6-4
TR bit in CCOM 5-9
TRTDL – transmission request/DLC register 5-20
DLC3-DLC0 – data length code bits 5-20
ID2-ID0 – identifier bits 5-20
RTR – remote transmission request 5-20
TS bit in CSTAT 5-10
TSEG22-TSEG10 bits in CBT1 5-16
TSR – timer status register 6-6
ICF1, ICF2 – input capture flags 6-6
OCF1, OCF2 – output compare flags 6-6
TOF – timer overflow status flag 6-6
TX0, TX1 2-17
V
VDD, VSS 2-11
VDD1, VSS1 2-17
VDDH 2-17
VPP1 2-16
VPP6 B-2
VRH 2-16
VRL 2-16
W
WAIT 2-7
WAKE bit in SCCR1 7-11
watchdog – see COP
, WDOG bit in Miscellaneous 3-12 10-4
WIF bit in CINT 5-12
wired-OR interrupt – see WOI
WOI 10-11
WOI bit in MOR B-12
WOIE bit in EEPROM control B-8
WWAT bit in MOR B-13
MC68HC05X16
Rev. 1
INDEX
MOTOROLA
ix