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HC05 Datasheet, PDF (140/232 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit | |||
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10
Table 10-1 Effect of RESET, POR, STOP and WAIT
Function/effect
RESET POR WAIT STOP
Timer prescaler cleared
x
x
â
â
Timer counter set to $FFFC
x
x
â
â
All timer enable bits cleared (disable)
x
x
â
â
Data direction registers cleared (inputs) x
x
â
â
Stack pointer set to $00FF
x
x
â
â
Internal address bus forced to restart
x
x
â
â
Vector $3FFE, $3FFF
x
x
â
â
Interrupt mask bit (I-bit CCR) set
x
x
â
â
Interrupt mask bit (I-bit CCR) cleared
â
â
x
x
Interrupt enable bit (INTE) set
x
x
â
â
POR bit in miscellaneous register set
â
x
â
â
STOP latch reset
x
x
â
â
IRQ latch reset
x
x
â
â
WAIT latch reset
x
x
â
â
SCI disabled
x
x
â
â
SCI status bits cleared (except TDRE
and TC)
x
x
â
â
SCI interrupt enable bits cleared
x
x
â
â
SCI status bits TDRE and TC set
x
x
â
â
Oscillator disabled for 4064 cycles
â
x
â
x
Timer clock cleared
â
x
â
x
SCI clock cleared
â
x
â
x
A/D disabled
x
x
â
x
SM bit in the miscellaneous register
cleared
x
x
â
x
Watchdog counter reset
x
x
x
x
WDOG bit in the miscellaneous register
reset
x
x
â
x
EEPROM control bits set or cleared (as
per Section 3.5.1)
x
x
â
x
x = Described action takes place
â = Described action does not take
place
MOTOROLA
10-6
RESETS AND INTERRUPTS
MC68HC05X16
Rev. 1
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