HC05 Datasheet, PDF(102/232 Page) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

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HC05 Datasheet, PDF (102/232 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

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Internal

processor clock

Internal

timer clocks

ï£± T00

ï£´

ï£²

T01

ï£´ T10

ï£³ T11

16-bit

counter

Output compare

register

$F456

(Note 1)

CPU writes $F457

$F457

$F458

$F457

$F459

Compare register

latch

(Note 1)

6

Output compare

ï¬ag and TCMP1,2

(Note 2)

Note:

The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state

T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.

Figure 6-4 Timer state timing diagram for output compare

Internal

processor clock

Internal

timer clocks

ï£± T00

ï£´

ï£²

T01

ï£´ T10

ï£³ T11

16-bit

counter

$FFFF

$0000

$0001

$0002

Timer overï¬ow

ï¬ag

Note:

The timer overï¬ow ï¬ag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by

a read of the timer status register during the internal processor clock high time, followed by a read of the

counter low register.

Figure 6-5 Timer state timing diagram for timer overï¬ow

MOTOROLA

6-14

PROGRAMMABLE TIMER

MC68HC05X16

Rev. 1

▷