MC68HC68T1 Datasheet, PDF (7/26 Pages) Motorola, Inc – Real-Time Clock plus RAM with Serial Interface

FREEZE FUNCTION
The freeze function prevents an increment of the time
counters, if any of the registers are being read. Also, alarm
operation is delayed if the registers are being read. This
causes the clock to lose time with increasing rates of accel-
eration.
POWER SENSING
When power sensing is enabled (Power Sense Bit in the
interrupt control register), ac/dc transitions are sensed at the
LINE input pin. Threshold detectors determine when tran-
sitions cease. After a delay of 2.68 to 4.64 ms plus the exter-
nal input RC circuit time constant, an interrupt true bit is set
high in the status register. This bit can then be sampled to
see if system power has turned back on (see Figure 8).
The power–sense circuitry operates by sensing the level of
the voltage present at the LINE input pin. This voltage is cen-
tered around VDD, and as long as the voltage is either plus or
minus a threshold (approximately 0.7 V) from VDD, a power
sense failure is not indicated. With an ac signal present,
remaining in this VDD window longer than a maximum of
4.64 ms activates the power–sense circuit. The larger the
amplitude of the signal, the less likely a power failure would
be detected. A 50 or 60 Hz, 10 V p–p sine–wave voltage is
an acceptable signal to present at the LINE input pin to set
up the power–sense function. When ac power fails, an inter-
nal circuit pulls the voltage at the line pin within the detection
window.
Power–Down
Power–down is a processor–directed operation. The
power–down bit is set in the interrupt control register to initi-
ate power–down operation. During power–down, the power
supply enable (PSE) output, normally high, is driven low. The
CLKOUT pin is driven low. The CPUR output, connected to
the processor reset input pin, is also driven low. In addition,
the serial interface (MOSI and MISO) is disabled (see Fig-
ure 9).
Power–Up
There are four methods that can initiate the power–up
mode. Two of the methods require an interrupt to the micro-
controller or processor by programming the interrupt control
register. The interrupts can be generated by the alarm circuit
by setting the alarm bit and the appropriate alarm registers.
Also, an interrupt can be generated by programming the peri-
odic interrupt bits in the interrupt control register. VSYS must
be at 5 volts for this operation to occur.
The third method is by initiating the power sense circuit
with the power sense bit in the interrupt control register set to
sense power loss along with the VSYS pin to sense subse-
quent power–up condition (see Figure 10). (Reference Fig-
ure 19 for application circuit for third method.)
The fourth method that initiates power–up occurs when the
level on the VSYS pin rises 0.7 V above the level of the VBATT
pin, after previously falling to the level of VBATT while in the
battery–backup mode. An interrupt is not generated when
the fourth method is utilized.
While in the single–supply mode, power–up is initiated
when the VSYS pin loses power and then returns high. There
is no interrupt generated when using this method (see Fig-
ure 11).
MOTOROLA
MC68HC68T1
7