MC68HC68T1 Datasheet, PDF (14/26 Pages) Motorola, Inc – Real-Time Clock plus RAM with Serial Interface

LINE
Line Sense (Pin 11)
The LINE sense input can be used to drive one of two
functions. The first function utilizes the input signal as the fre-
quency source for the timekeeping counters. This function is
selected by setting the line/XTAL bit high in the clock control
register. The second function enables the LINE input to de-
tect a power failure. Threshold detectors operating above
and below VDD sense an ac voltage loss. The Power Sense
bit in the interrupt control register must be set high, and
crystal or external clock source operation is required. The
line/XTAL bit in the clock control register must be low to
select crystal operation. When Power Sense is enabled, this
pin, left unconnected, floats to VDD.
This output has no ESD protection diode tied to VDD which
allows this pin’s voltage to rise above VDD. Care must be
taken in the handling of this device.
VSYS
System Voltage (Pin 12)
This input is connected to system voltage. The level on this
pin initiates power–up if it rises 0.7 V above the level at the
VBATT input pin after previously falling below 0.7 V below
VBATT. When power–up is initiated, the PSE pin returns high
and the CLKOUT pin is enabled. The CPUR output pin is
also set high. Conversely, if the level of the VSYS pin falls be-
low VBATT + 0.7 V, the PSE, CLKOUT, and CPUR pins are
placed low. The voltage level present at this pin at the end of
POR determines the device’s operating mode.
VBATT
Battery Voltage (Pin 13)
This pin is the only oscillator power source and should be
connected to the positive terminal of the battery. The VBATT
pin always supplies power to the MC68HC68T1, even when
the device is not in the battery–backup mode. To maintain
timekeeping, the VBATT pin must be at least 2.2 V. When the
level on the VSYS pin falls below VBATT + 0.7 V, VBATT is
internally connected to the VDD pin.
When the LINE input is used as the frequency source,
the unused VBATT and XTAL pins may be tied to VSS.
Alternatively, if VBATT is connected to VDD, XTALin can be
tied to either VSS or VDD.
This output has no ESD protection diode tied to VDD which
allows this pin’s voltage to rise above VDD. Care must be
taken in the handling of this device.
XTALin, XTALout
Crystal Input/Output (Pins 14, 15)
For crystal operation, these two pins are connected to a
32.768 kHz, 1.048576 MHz, 2.097152 MHz, or 4.194304 MHz
crystal. If crystal operation is not desired and Line Sense is
used as frequency source, connect XTALin to VDD or VSS
(caution: see VBATT pin description) and leave XTAout open.
If an external clock is used, connect the external clock to
XTALin and leave XTALout open. The external clock must
swing from at least 30 to 70% of (VDD – VSS). Preferably, this
input should swing from VSS to VDD.
MC68HC68T1
14
VDD
Positive Power Supply (Pin 16)
For full functionality, the positive power supply pin may
range from 3.0 to 6.0 V with respect to VSS. To maintain time-
keeping, the minimum standby voltage is 2.2 V with respect
to VSS. For proper operation in battery–backup mode, a
diode must be placed in series with VDD.
CAUTION
Data transfer to/from the MC68HC68T1 must not
be attempted if the supply voltage falls below
3.0 V.
REGISTERS
CLOCK CONTROL REGISTER (READ/WRITE) — READ
ADDRESS $31/WRITE ADDRESS $B1
MSB
D7
START
STOP
D6
LINE
XTAL
LSB
D5
D4 D3 D2 D1 D0
XTAL XTAL 50 Hz CLK CLK CLK
SELECT SELECT
OUT OUT OUT
1
0 60 Hz 2 1 0
All bits are reset low by a power–on reset.
Start–Stop
A high written into this bit enables the counter stages of
clock circuitry. A low holds all bits reset in the divider chain
from 32 Hz to 1 Hz. The clock out signal selected by bits D0,
D1, and D2 is not affected by the stop function except the
1 and 2 Hz outputs.
Line/ XTAL
When this bit is high, clock operation uses the 50 or 60
cycle input present at the LINE input pin. When the bit is low,
the XTALin pin is the source of the time update.
XTAL Select
Accommodation of one of four possible crystals are se-
lected by the value in bits D4 and D5.
0 = 4.194304 MHz 2 = 1.048576 MHz
1 = 2.097152 MHz 3 = 32.768 kHz
W The MC68HC68T1 has an on–chip 150 k resistor that is
switched in series with the internal inverter when 32 kHz is
selected via the clock control register. At power–up, the de-
vice sets up for a 4 MHz oscillator and the series resistor is
not part of the oscillator circuit. Until this resistor is switched
in, oscillations may be unstable with the 32 kHz crystal. (See
Figure 12.)
XTALin
5 – 30 pF _C1
R1
R2
C2 10 – 40 pF
XTALout
REAL–TIME CLOCK
MC68HC68T1
Figure 12. Recommended Oscillator Circuit
(C1, C2 Values Depend Upon the Crystal Frequency)
MOTOROLA