MC68HC68T1 Datasheet, PDF (6/26 Pages) Motorola, Inc – Real-Time Clock plus RAM with Serial Interface

OPERATING CHARACTERISTICS
The real–time clock consists of a clock/calendar and a
32 x 8 RAM (see Figure 5). Communication with the device
may be established via a serial peripheral interface (SPI) or
MICROWIRE bus. In addition to the clock/calendar data from
seconds to years, and systems flexibility provided by the
32–byte RAM, the clock features computer handshaking with
an interrupt output and a separate square–wave clock output
that can be one of seven different frequencies. An alarm cir-
cuit is available that compares the alarm latches with the se-
conds, minutes, and hours time counters and activates the
interrupt output when they are equal. The clock is specifically
designed to aid in power–up/power–down applications and
offers several pins to aid the designer of battery–backup sys-
tems.
CLOCK/CALENDAR
The clock/calendar portion of this device consists of a long
string of counters that is toggled by a 1 Hz input. The 1 Hz
input is derived from the on–chip oscillator that utilizes one of
four possible external crystals or that can be driven by an ex-
ternal frequency source. The 1 Hz trigger to the counters can
also be supplied by a 50 or 60 Hz source that is connected to
the LINE input pin.
The time counters offer seconds, minutes, and hours data
in 12– or 24–hour format. An AM/PM indicator is available
that once set, toggles at 12:00 AM and 12:00 PM. The calen-
dar counters consist of day of week, date of month, month,
and year information. Data in the counters is in BCD format.
The hours counter utilizes BCD for hours data plus bits for
12/24 hour and AM/PM modes. The seven time counters are
read serially at addresses $20 through $26. The time count-
ers are written to at addresses $A0 through $A6. (See Fig-
ures 5 and 6 and Table 1.)
32 x 8 GENERAL–PURPOSE RAM
The real–time clock also has a static 32 x 8 RAM. The
RAM is read at addresses $00 through $1F and written to at
addresses $80 through $9F (see Figure 5).
ALARM
The alarm is set by accessing the three alarm latches and
loading the desired data. (See Serial Peripheral Interface.)
The alarm latches consist of seconds, minutes, and hours
registers. When their outputs equal the values of the se-
conds, minutes, and hours time counters, an interrupt is gen-
erated. The interrupt output goes low if the alarm bit in the
status register is set and the interrupt output is activated after
an alarm time is sensed (see Pin Descriptions, INT Pin). To
preclude a false interrupt when loading the time counters, the
alarm interrupt bit in the interrupt control register should be
reset. This procedure is not required when the alarm time is
being loaded.
WATCHDOG FUNCTION
When Watchdog (bit 7) in the interrupt control register is
set high, the clock’s slave select pin must be toggled at regu-
lar intervals without a serial data transfer. If SS is not toggled
at the rate shown in Table 2, the MC68HC68T1 supplies a
CPU reset pulse at Pin 2 and Watchdog (bit 6) in the status
register is set (see Figure 7). Typical service and reset times
are shown in Table 2.
CLOCK OUT
The value in the three least significant bits of the clock
control register selects one of seven possible output fre-
quencies. (See Clock Control Register.) This square–wave
signal is available at the CLKOUT pin. When the power–
down operation is initialized, the output is reset low.
CONTROL REGISTER AND STATUS REGISTER
The operation of the real–time clock is controlled by the
clock control and interrupt control registers, which are read/
write registers. Another register, the status register, is avail-
able to indicate the operating conditions. The status register
is a read–only register, and a read operation resets status
bits.
MODE SELECT
The voltage level that is present at the VSYS input pin at the
end of power–on reset selects the device to be in the single–
supply mode or battery–backup mode.
Single–Supply Mode
If VSYS is powered up when power–on reset is completed;
CLKOUT, PSE, and CPUR are enabled high and the device
is completely operational. CPUR is asserted low if the volt-
age level at the VSYS pin subsequently falls below VBATT +
0.7 V. If CLKOUT, PSE, and CPUR are reset low due to a
power–down instruction, VSYS brought low and then pow-
ered high re–enables these outputs.
An example of the single–supply mode is where only one
supply is available and VDD, VBATT, and VSYS are tied to-
gether to the supply.
Battery–Backup Mode
If VSYS is not powered up (VSYS = 0 V) at the end of pow-
er–on reset, CLKOUT, PSE, CPUR, and SS are disabled
(CLKOUT, PSE, and CPUR low). This condition is held until
VSYS rises to a threshold (approximately 0.7 V) above VBATT.
CLKOUT, PSE, and CPUR are then enabled and the device
is operational. If VSYS falls below a threshold above VBATT,
the outputs CLKOUT, PSE, and CPUR are reset low.
An example of battery–backup operation occurs if VSYS is
tied to the 5 V supply and is not receiving voltage from a sup-
ply. A rechargeable battery is connected to the VBATT pin,
causing a POR while VSYS = 0 V. The device retains data
and keeps time down to a minimum VBATT voltage of 2.2 V.
The power consumption may not settle to the specified lim-
it until main power is cycled once.
POWER CONTROL
Power control is composed of two operations, power–
sense and power–down/power–up. Two pins are involved in
power sensing, the LINE input pin and the INT output pin.
Two additional pins, PSE and VSYS, are utilized during
power–down/power–up operation.
MC68HC68T1
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MOTOROLA