MC68HC68T1 Datasheet, PDF (15/26 Pages) Motorola, Inc – Real-Time Clock plus RAM with Serial Interface

W Resistor R1 is recommended to be 10 M for 32 kHz
operation. Consult crystal manufacturer for R1 value for oth-
er frequencies. Resistor R2 must be used in 32 kHz opera-
W tion only. Use a 200 to 300 k range. This stabilizes the
oscillator until the control register is set properly and reduces
standby current.
50 Hz – 60 Hz
50 Hz may be used as the input frequency at the LINE in-
put when this bit is set high; a low accommodates 60 Hz. The
power sense bit in the interrupt control register must be reset
low for line frequency operation.
Clock Out
Three bits specify one of the seven frequencies to be used
as the square–wave clock output (CLKOUT).
0 = XTAL
1 = XTAL/2
2 = XTAL/4
3 = XTAL/8
4 = Disable (low output)
5 = 1 Hz
6 = 2 Hz
7 = 50/60 Hz for LINE operation
7 = 64 Hz for XTAL operation
All bits in the clock control register are reset by a power–on
reset. Therefore, XTAL is selected as the clock output at this
time.
INTERRUPT CONTROL REGISTER (READ/WRITE) —
READ ADDRESS $32/WRITE ADDRESS $B2
MSB
LSB
D7
D6
D5
D4 D3 D2 D1 D0
WATCH– POWER– POWER
DOG DOWN SENSE
ALARM
PERIODIC SELECT
All bits are reset low by power–on reset.
Watchdog
When this bit is set high, the watchdog operation is en-
abled. This function requires the CPU to toggle the SS pin
periodically without a serial transfer requirement. In the event
this does not occur, a CPU reset is issued at the CPUR pin.
The status register must be read before re–enabling the
watchdog function.
Power–Down
A high in this location initiates a power–down. A CPU reset
occurs via the CPUR output, the CLKOUT and PSE output
pins are reset low, and the serial interface is disabled.
Power Sense
When set high, this bit is used to enable the LINE input pin
to sense a power failure. When power sense is selected, the
input to the 50/60 Hz prescaler is disconnected; therefore,
crystal operation is required. An interrupt is generated when
a power failure is sensed and the power sense and interrupt
true bit in the status register are set. When power sense is
activated, a logic low must be written to this location followed
by a high to re–enable power sense.
Alarm
The output of the alarm comparator is enabled when this
bit is set high. When an equal comparison occurs between
the seconds, minutes, and hours time counters and alarm
latches, the interrupt output is activated. When loading the
time counters, this bit should be reset low to avoid a false in-
terrupt. This is not required when loading the alarm latches.
See INT pin description for explanation of alarm delay.
Periodic Select
The value in these four bits (D0, D1, D2, and D3) selects
the frequency of the periodic output (see Table 3).
Table 3. Periodic Interrupt Output Frequencies
(at INT Pin)
D3 – D0
Value
(Hex)
Periodic Interrupt
Output Frequency
Frequency Timebase
XTAL
Line
0
Disable
1
2048 Hz
X
2
1024 Hz
X
3
512 Hz
X
4
256 Hz
X
5
128 Hz
X
6
64 Hz
X
50 or 60 Hz
X
7
32 Hz
X
8
16 Hz
X
9
8 Hz
X
A
4 Hz
X
B
2 Hz
X
X
C
1 Hz
X
X
D
1 Cycle per Minute
X
X
E
1 Cycle per Hour
X
X
F
1 Cycle per Day
X
X
STATUS REGISTER (READ ONLY) — ADDRESS $30
MSB
D7 D6 D5 D4
0
WATCH–
DOG
0
FIRST
TIME–
UP
D3
INTER-
RUPT
TRUE
D2
POWER
SENSE
INT
D1
ALARM
INT
LSB
D0
CLOCK
INT
NOTE
All bits are reset low by a power–on reset except
the first time–up bit which is set high. All bits ex-
cept the power sense bit are reset after a read of
the status register.
Watchdog
If this bit is set high, the watchdog circuit has detected a
CPU failure.
First Time–Up
Power–on reset sets this bit high. This signifies the data in
the RAM and Clock is not valid and should be initialized.
MOTOROLA
MC68HC68T1
15