M68HC11 Datasheet, PDF (42/336 Pages) Motorola, Inc – Technical Data

Pin Descriptions
2.13.3 Port C
While in single-chip operating modes, all port C pins are
general-purpose I/O pins. Port C inputs can be latched into an alternate
PORTCL register by providing an input transition to the STRA signal.
Port C can also be used in full handshake modes of parallel I/O where
the STRA input and STRB output act as handshake control lines.
When in expanded multiplexed modes, all port C pins are configured as
multiplexed address/data signals. During the address portion of each
MCU cycle, bits 7–0 of the address are output on the PC7–PC0 pins.
During the data portion of each MCU cycle (E high), PC7–PC0 are
bidirectional data signals, DATA7–DATA0. The direction of data at the
port C pins is indicated by the R/W signal.
The CWOM control bit in the PIOC register disables the port C P-channel
output driver. CWOM simultaneously affects all eight bits of port C.
Because the N-channel driver is not affected by CWOM, setting CWOM
causes port C to become an open-drain type output port suitable for
wired-OR operation.
In wired-OR mode:
• When a port C bit is at logic level 0, it is driven low by the
N-channel driver.
• When a port C bit is at logic level 1, the associated pin has
high-impedance, as neither the N-channel nor the P-channel
devices are active.
It is customary to have an external pullup resistor on lines that are driven
by open-drain devices. Port C can only be configured for wired-OR
operation when the MCU is in single-chip mode. Refer to Section 6.
Parallel Input/Output (I/O) Ports for additional information about port C
functions.
Technical Data
42
Pin Descriptions
MC68HC11E Family — Rev. 4
MOTOROLA