M68HC11 Datasheet, PDF (312/336 Pages) Motorola, Inc – Technical Data

Application Note
Between these times, the bootloader program is executed, which
changes the states of some systems and control bits:
• The SCI system is initialized and turned on (Rx and Tx).
• The SCI system has control of the PD0 and PD1 pins.
• Port D outputs are configured for wire-OR operation.
• The stack pointer is initialized to the top of RAM.
• Time has passed (two or more SCI character times).
• Timer has advanced from its reset count value.
Users also forget that bootstrap mode is a special mode. Thus,
privileged control bits are accessible, and write protection for some
registers is not in effect. The bootstrap ROM is in the memory map. The
DISR bit in the TEST1 control register is set, which disables resets from
the COP and clock monitor systems.
Since bootstrap is a special mode, these conditions can be changed by
software. The bus can even be switched from single-chip mode to
expanded mode to gain access to external memories and peripherals.
Connecting RxD
to V_SS Does Not
Cause the SCI
to Receive a Break
To force an immediate jump to the start of EEPROM, the bootstrap
firmware looks for the first received character to be $00 (or break). The
data reception logic in the SCI looks for a 1-to-0 transition on the RxD
pin to synchronize to the beginning of a receive character. If the RxD pin
is tied to ground, no 1-to-0 transition occurs. The SCI transmitter sends
a break character when the bootloader firmware starts, and this break
character can be fed back to the RxD pin to cause the jump to EEPROM.
Since TxD is configured as an open-drain output, a pullup resistor is
required.
$FF Character Is
Required before
Loading into RAM
The initial character (usually $FF) that sets the download baud rate is
often forgotten.
AN1060 — Rev. 1.0
312
MOTOROLA