M68HC11 Datasheet, PDF (188/336 Pages) Motorola, Inc – Technical Data

Timing System
high-order byte of an output compare register pair inhibits the output
compare function for one bus cycle. This inhibition prevents
inappropriate subsequent comparisons. Coherency requires a complete
16-bit read or write. However, if coherency is not needed, byte accesses
can be used.
For output compare functions, write a comparison value to output
compare registers TOC1–TOC4 and TI4/O5. When TCNT value
matches the comparison value, specified pin actions occur.
Register name: Timer Output Compare 1 Register (High) Address: $1016
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Write:
Reset: 1
1
1
1
1
1
1
1
Register name: Timer Output Compare 1 Register (Low) Address: $1017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 9-8. Timer Output Compare 1 Register Pair (TOC1)
Technical Data
188
Register name: Timer Output Compare 2 Register (High) Address: $1018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Write:
Reset: 1
1
1
1
1
1
1
1
Register name: Timer Output Compare 2 Register (Low) Address: $1019
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 9-9. Timer Output Compare 2 Register Pair (TOC2)
Timing System
MC68HC11E Family — Rev. 4
MOTOROLA