M68HC11 Datasheet, PDF (193/336 Pages) Motorola, Inc – Technical Data

Timing System
Output Compare
9.5.5 Timer Counter Register
The 16-bit read-only TCNT register contains the prescaled value of the
16-bit timer. A full counter read addresses the most significant byte
(MSB) first. A read of this address causes the least significant byte (LSB)
to be latched into a buffer for the next CPU cycle so that a double-byte
read returns the full 16-bit state of the counter at the time of the MSB
read cycle.
Register name: Timer Counter Register (High) Address: $100E
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Register name: Timer Counter Register (Low) Address: $100F
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-15. Timer Counter Register (TCNT)
MC68HC11E Family — Rev. 4
MOTOROLA
Timing System
Technical Data
193