M68HC11 Datasheet, PDF (137/336 Pages) Motorola, Inc – Technical Data

Parallel Input/Output (I/O) Ports
Port C
Address: $1005
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PCL7
Write:
PCL6
PCL5
PCL4
PCL3
PCL2
PCL1
PCL0
Reset:
Indeterminate after reset
Figure 6-5. Port C Latched Register (PORTCL)
PORTCL is used in the handshake clearing mechanism. When an active
edge occurs on the STRA pin, port C data is latched into the PORTCL
register. Reads of this register return the last value latched into PORTCL
and clear STAF flag (following a read of PIOC with STAF set).
Address: $1007
Bit 7
6
5
4
3
2
1
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1
Write:
Reset: 0
0
0
0
0
0
0
Figure 6-6. Port C Data Direction Register (DDRC)
Bit 0
DDRC0
0
DDRC[7:0] — Port C Data Direction Bits
In handshake output mode, DDRC bits select the 3-stated output
option (DDCx = 1).
0 = Input
1 = Output
MC68HC11E Family — Rev. 4
MOTOROLA
Parallel Input/Output (I/O) Ports
Technical Data
137