MV20556 Datasheet, PDF (9/30 Pages) Mosel Vitelic, Corp – 8 - Bit MCU Mouse Controller

MOSEL VITELIC INC.
Preliminary
MV20556
Interrupt System
A sophisticated multiple-source, two-priority-level,
nested interrupt system is provided. The interrupt
system is shown as below diagram. The interrupt
request flag and program memory location of interrupt
service program is shown in table on next page.
Five interrupt sources
Each interrupt can be individually enabled/disabled
Enabled interrupts can be globally enabled/disabled
Each interrupt can be assigned to either of two
priority levels
Each interrupt vectors to a separate location in
program memory
Interrupt nesting to two levels
External interrupt requests can be programmmed to
be level- or transition- activated
Interrupt Overall
External events and the real-time driven onchip
peripherals require service by the CPU asynchronous
to the execution of any particular section of code. To
tie the asynchronous activities of these functions to
normal program execution, a sophisticated
multiple-source, two-priority-level, nested interrupt
system is provided. Interrupt response latency ranges
from 3µs to 7µs when using a 12 MHz crystal.
The MV20556 acknowledges interrupt requests from
five sources: Two from external sources via the #INT0
and INT1 pins, one from each of the two internal
counters and one from the serial I/O port. Each
interrupt vectors to a separate location in Program
Memory for its service program. Each of the five
sources can be assigned to either of two priority levels
and can be independently enabled and disabled.
Additionally all enabled sources can be globally
disabled or enabled. Each external interrupt is
programmable as either level- or transition-activated
and is active-low to allow the "wire or-ing" of several
interrupt sources to the input pin. The interrupt system
is shown diagrammatically in below figure.
Interrupt System Functional Description
Interrupts result in a transfer of control to a new
program location. The program servicing the request
begins at this address. In the MV20556 there are five
hardware sources that can generate an interrupt
request. The starting address of the interrupt service
program for each interrupt source is shown in table on
next page.
A resource requests an interrupt by setting its
associated interrupt request flag in the TCON or SCON
register, as detailed in following table. The interrupt
request will be acknowledged if its interrupt enable bit
in the Interrupt Enable register is set and if it is the
highest priority resource requesting an interrupt. A
resource's interrupt priority level is established as
INPUT LEVEL AND
INTERRUPT REQUEST
FLAG REGISTER:
TCON.1
IE0
TCON.5
TF0
TCON.3
IE1
TCON.7
TF1
SCON.0
TI
SCON.1
RX
SOURCE
ENABLE
IE.0
EX0
IE.1
ET0
IE.2
EX1
IE.3
ET1
IE.4
ES
GLOBAL
ENABLE
IE.7
EA
INTERRUPT
PRIORITY
REGISTER:
IP.0
PX0
IP.1
PT0
IP.2
PX1
IP.3
PT1
IP.4
PS
POLLING
HARDWARE
SOURCE
I.D.
HIGH PRIORITY
INTERRUPT
REQUEST
VECTOR
SOURCE
I.D.
LOW PRIORITY
INTERRUPT
REQUEST
VECTOR
Specifications subject to change without notice, contact your sales representatives for the most recent information.
9/27
PID256** 07/97