MV20556 Datasheet, PDF (14/30 Pages) Mosel Vitelic, Corp – 8 - Bit MCU Mouse Controller

MOSEL VITELIC INC.
Preliminary
MV20556
Timer/Counter (Cont'd)
the counter. This mode is provided as an alternative to
use TR1 bit (TCON.6) to start and stop counter 1. The
serial port receives a pulse each time that counter 1
overflows. The standard UART modes divide this pulse
rate to generate the transmission rate.
mode 3: stop
Counter 0/Timer 0
Counter 0/Timer 0 can also be configured in one of four
modes software program code on the fly:
Mode 0-2:
Mode 0-2 are the same as those for counter 1.
Mode 3: 8-bit timer/counter (TL1)
In mode 3, the configuration of TH0 is not affected by
the bits in TMOD or TCON. It is configured solely as
an 8-bit timer that is enabled for incrementing by
TCON's TR1 bit. Upon TH0's overflows, the TF1 flag
gets set. Thus, neither TR1 nor TF1 is available to
counter 1 when counter 0 is in mode 3. The function of
TR1 can be done by placing counter 1 in mode 3, so
only the function of TF1 is actually given up by counter
1. In mode 3, TL0 is configured as an 8-bit
timer/counter and is controlled, as usual, by the GATE
(TMOD.3), C/#T(TMOD.2), TR0 (TCON.4) and TF0
(TCON.5) control bits.
Configuring of Timer/Counter
The use of the timer/counters is determined by two 8-
bit registers, TMOD (timer mode) and TCON (timer
control). The input to the counter circuitry from an
external reference (for use as a counter), or from the
on-chip oscillator (for use as a counter), or from the on-
chip oscillator (for use as a timer), depending on whether
TMOD's C/#T bit is set or cleared, respectively. When
used as a timer base, the on-chip oscillator frequency is
divided by twelve (12) before being input to the counter
circuitry. When TMOD's Gate bit is set (1), the external
reference input (T1, T0) or the oscillator input is gated to
the counter conditional upon a second external input
(#INT0, #INT1) being high. When the Gate bit is zero (0),
the external reference or oscillator input is unconditionally
enabled. In either case, the normal interrupt function of
#INT0 and #INT1 is not affected by the counter's
operation. If enabled, an interrupt will occur when the
input at #INT0 or #INT1 is low. The counters are enabled
for incrementing when TCON's TR1 and TR0 bits are set.
When the counters overflow the TF1 and TF0 bits in
TCON get set and interrupt requests are generated. The
functions of the bits in TCON are shown in below table.
The functions of the bits in TMOD are shown in table on
next page.
Operation
The counter circuitry counts up to all 1's and then
overflows to either 0's or the reload value. Upon
overflow, TF1 or TF0 gets set. When an instruction
MSB
TF1 TR1 TF0 TR0
-
LSB
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IDF
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TF1
TCON.7 Timer 1 overflow flag. Set by hardware when the timer/counter 1 overflows. Cleared by hardware as
processor vectors to the interrupt service routine.
TR1
TCON.6 Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 ON/OFF.
TF0
TCON.5 Timer 0 overflow flag. Set by hardware when the timer/counter 0 overflows. Cleared by hardware as
processor vectors to the interrupt service routine.
TR0
TCON.4 Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 ON/OFF.
IE1
TCON.3 Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
processed.
IT1
TCON.2 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.
IE0
TCON.1 Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
processed.
IT0
TCON.0 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.
TCON definition
Specifications subject to change without notice, contact your sales representatives for the most recent information.
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