MV20556 Datasheet, PDF (17/30 Pages) Mosel Vitelic, Corp – 8 - Bit MCU Mouse Controller

MOSEL VITELIC INC.
Preliminary
MV20556
External Interface (Cont'd)
Idle Mode
During idle mode, the CPU is stopped but below blocks
are kept functioning:clock generator, RAM, timer/
counters, serial port and interrupt block.
During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/
counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing instructions.
In Idle mode (IDL=1), the oscillator continues to run and
the interrput, and timer blocks continue to be clocked but
the clock signal is gated off to the CPU. The activities of
the CPU no longer exist unless waiting for an interrupt
request.
-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.
-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.
-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.
-There are two ways to terminate the Idle Mode.
1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.
2) By hardware reset
Since the clock oscillator is still running, the hardware
reset needs to be held active for only two machine
cycles (24 clocks) to complete the reset. All
SFR and PC value will be cleared to reset value.
After the program wakes up, the PC value will be 0023h
(if enable IE register) and execute interrupt service
Vdd
#INTx
(power fail)
RES
Interrupt
Normal
service
Operation routine
Normal
Operation
routine and then returns to PC+1 address after the
program wakes up.
Power Down Mode
It saves the RAM content, stops the clock generator and
disables every other blocks' function until the coming
hardware reset. To save even more power consumption,
user's software program can invoke this mode. The
SFRs and the on-chip data RAM retain their values
during this mode, but the porcessor stops executing
instructions. In Power-Down mode (PD=1) the oscillator
is frozen.
-An instruction that sets flag (PCON.1) causes that to
be the last instruction executed before going into the
Power Down Mode.
-In the Power Down Mode, the on-chip oscillator is
stopped.
With the clock frozen, all functions are stopped, but
the on-chip RAM and Special Function Registers are
held.
-Reset redefines all the SFRs, but does not change the
on-chip RAM.
-There is only one way to terminate the Power Down
Mode - by hardware reset.
All SFR and PC value will be cleared to reset value.
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
-Care must be taken, however, to ensure that Vdd is
not reduced before the Power Down Mode is invoked,
and that Vdd is restored to its normal operating level
before the Power Down Mode is terminated.
-The hardware reset must be held active long enough
to allow the oscillator to restart and stabilize.
Data can be maintained valid in the Internal Data RAM
while the remainder of the MV20556 is powered down.
When powered down, the MV20556 consumes about
10% of normal operating power. During normal operation
both the CPU and the internal RAM derive their power
from VDD. However, the internal RAM will derive its
power from RES when the voltage on VDD is more than
a diode drop below that on RES.
When a power-supply failure is imminent, the user's
system generates a "power-failure" signal to interrupt the
Mode
Idle
Power Down
Program
memory
Internal
Internal
Port 3
Data
Data
Specifications subject to change without notice, contact your sales representatives for the most recent information.
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PID256** 07/97