M38027E8SP Datasheet, PDF (46/51 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
Parameter
tsu(ONW–φ)
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
tsu(ONW–RD)
tsu(ONW–WR)
th(RD–ONW)
th(WR–ONW)
tsu(DB–RD)
th(RD–DB)
Before φ ONW input set up time
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
Before RD ONW input set up time
Before WR ONW input set up time
After RD ONW input hold time
After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time
Limits
Unit
Min. Typ. Max.
–20
ns
–20
ns
60
ns
0
ns
–20
ns
–20
ns
65
ns
0
ns
SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–WR)
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
twL(RD)
twL(WR)
Parameter
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
RD and WR delay time
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(when one wait is valid)
Test conditions
Fig. 36
Limits
Min.
Typ.
Max. ^Unit
2!tc(XIN)
ns
tc(XIN)–10
ns
tc(XIN)–10
ns
20
40 ns
6
10
ns
25
45 ns
6
10
ns
20
ns
10
ns
10
20 ns
3
5
10 ns
20
70 ns
15
ns
tc(XIN)–10
ns
3tc(XIN)–10
ns
td(AH–RD)
td(AH–WR)
After AD15–AD8 RD delay time
After AD15–AD8 WR delay time
tc(XIN)–35 tc(XIN)–15
ns
td(AL–RD)
td(AL–WR)
After AD7–AD0 RD delay time
After AD7–AD0 WR delay time
tc(XIN)–40 tc(XIN)–20
ns
tv(RD–AH)
tv(WR–AH)
After RD AD15–AD8 valid time
After WR AD15–AD8 valid time
0
5
ns
tv(RD–AL)
tv(WR–AL)
td(WR–DB)
tv(WR–DB)
td(RESET–RESETOUT)
tv(φ–RESET)
After RD AD7–AD0 valid time
After WR AD7–AD0 valid time
After WR data bus delay time
After WR data bus valid time
RESETOUT output delay time
RESETOUT output valid time (Note 1)
0
5
ns
15
65 ns
10
ns
200 ns
0
200 ns
Note 1: The RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
Measurement output pin
100pF
CMOS output
Fig. 36 Circuit for measuring output switching
characteristics
46