M38027E8SP Datasheet, PDF (40/51 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tsu(ONW–φ)
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
tsu(ONW–RD)
tsu(ONW–WR)
th(RD–ONW)
th(WR–ONW)
tsu(DB–RD)
th(RD–DB)
Before φ ONW input set up time
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
Before RD ONW input set up time
Before WR ONW input set up time
After RD ONW input hold time
After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time
Parameter
Limits
Unit
Min. Typ. Max.
–20
ns
–20
ns
60
ns
0
ns
–20
ns
–20
ns
65
ns
0
ns
SWITCHING CHARATERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tc(φ)
φ clock cycle time
twH(φ)
φ clock “H” pulse width
twL(φ)
φ clock “L” pulse width
td(φ–AH)
After φ AD15–AD8 delay time
tv(φ–AH)
After φ AD15–AD8 valid time
td(φ–AL)
After φ AD7–AD0 delay time
tv(φ–AL)
After φ AD7–AD0 valid time
td(φ–SYNC) SYNC delay time
tv(φ–SYNC) SYNC valid time
td(φ–WR)
RD and WR delay time
tv(φ–WR)
RD and WR valid time
td(φ–DB)
After φ data bus delay time
tv(φ–DB)
After φ data bus valid time
twL(RD)
twL(WR)
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
td(AH–RD)
td(AH–WR)
After AD15–AD8 RD delay time
After AD15–AD8 WR delay time
td(AL–RD)
td(AL–WR)
After AD7–AD0 RD delay time
After AD7–AD0 WR delay time
tv(RD–AH)
tv(WR–AH)
After RD AD15–AD8 valid time
After WR AD15–AD8 valid time
tv(RD–AL)
tv(WR–AL)
After RD AD7–AD0 valid time
After WR AD7–AD0 valid time
td(WR–DB) After WR data bus delay time
tv(WR–DB) After WR data bus valid time
td(RESET–RESETOUT) RESETOUT output delay time (Note 1)
tv(φ–RESET) RESETOUT output valid time (Note 1)
Test conditions
Fig. 36
Limits
Unit
Min.
Typ. Max.
2tc(XIN)
ns
tc(XIN)–10
ns
tc(XIN)–10
ns
20
40 ns
6
10
ns
25
45 ns
6
10
ns
20
ns
10
ns
10
20 ns
3
5
10 ns
20
70 ns
15
ns
tc(XIN)–10
ns
3tc(XIN)–10
ns
tc(XIN)–35 tc(XIN)–15
ns
tc(XIN)–40 tc(XIN)–20
ns
0
5
ns
0
5
ns
15
65 ns
10
ns
200 ns
0
200 ns
Note 1: The RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
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