M38027E8SP Datasheet, PDF (14/51 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by sixteen sources: seven external, eight internal,
and one software.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0 to INT4,
CNTR0, or CNTR1) is changed, the corresponding interrupt re-
quest bit may also be set. Therefore, please take following se-
quence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 1. Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
Priority
1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
INT0
2
FFFB16
FFFA16
INT1
Serial I/O1
reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
3
FFF916
FFF816
4
FFF716
FFF616
5
FFF516
FFF416
6
FFF316
FFF216
7
FFF116
FFF016
8
FFEF16
FFEE16
9
FFED16
FFEC16
10
FFEB16
FFEA16
CNTR1
11
FFE916
FFE816
Serial I/O2
12
FFE716
FFE616
INT2
13
FFE516
FFE416
INT3
14
FFE316
FFE216
INT4
15
FFE116
FFE016
A-D converter
16
FFDF16
FFDE16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1
data reception
At completion of serial I/O1
transfer shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O2
data transfer
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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