M38027E8SP Datasheet, PDF (41/51 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tsu(ONW–φ)
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
tsu(ONW–RD)
tsu(ONW–WR)
th(RD–ONW)
th(WR–ONW)
tsu(DB–RD)
th(RD–DB)
Before φ ONW input set up time
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
Before RD ONW input set up time
Before WR ONW input set up time
After RD ONW input hold time
After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time
Parameter
Limits
Min.
Typ. Max. ^Unit
–20
ns
–20
ns
180
ns
0
ns
–20
ns
–20
ns
185
ns
0
ns
SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min. ^Typ.
Max. ^Unit
tc(φ)
φ clock cycle time
2tc(XIN)
ns
twH(φ)
φ clock “H” pulse width
tc(XIN)–20
ns
twL(φ)
φ clock “L” pulse width
tc(XIN)–20
ns
td(φ–AH)
After φ AD15–AD8 delay time
150 ns
tv(φ–AH)
After φ AD15–AD8 valid time
10
15
ns
td(φ–AL)
After φ AD7–AD0 delay time
150 ns
tv(φ–AL)
After φ AD7–AD0 valid time
10
15
ns
td(φ–SYNC) SYNC delay time
40
ns
tv(φ–SYNC) SYNC valid time
20
ns
td(φ–WR)
RD and WR delay time
15
25
ns
tv(φ–WR)
RD and WR valid time
3
7
15
ns
td(φ–DB)
After φ data bus delay time
200 ns
tv(φ–DB)
twL(RD)
twL(WR)
After φ data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(when one-wait is valid)
15
ns
Fig. 36
tc(XIN)–20
ns
3tc(XIN)–20
ns
td(AH–RD)
td(AH–WR)
After AD15–AD8 RD delay time
After AD15–AD8 WR delay time
tc(XIN)–145
ns
td(AL–RD)
td(AL–WR)
After AD7–AD0 RD delay time
After AD7–AD0 WR delay time
tc(XIN)–145
ns
tv(RD–AH)
tv(WR–AH)
After RD AD15–AD8 valid time
After WR AD15–AD8 valid time
5
10
ns
tv(RD–AL)
tv(WR–AL)
After RD AD7–AD0 valid time
After WR AD7–AD0 valid time
5
10
ns
td(WR–DB) After WR data bus delay time
195 _ns
tv(WR–DB) After WR data bus valid time
10
ns
td(RESET–RESETOUT) RESETOUT output delay time (Note 1)
300 _ns
tv(φ–RESET) RESETOUT output valid time (Note 1)
0
300 _ns
Note1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
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