MYX4DDR364M16JT Datasheet, PDF (74/128 Pages) Micross Components – 8n-bit prefetch architecture

READ Operation (continued)
Data from any READ burst must be completed before a
subsequent WRITE burst is allowed. An example of a READ
burst followed by a WRITE burst for BL8 is shown in Figure 33
(page 76) (BC4 is shown in Figure 34 (page 77). To ensure
the READ data is completed before the WRITE data is on the
bus, the minimum READ-to-WRITE timing is RL + ^tCCD - WL
+ 2^tCK.
A READ burst may be followed by a PRECHARGE command
to the same bank, provided auto precharge is not activated.
The minimum READ-to-PRECHARGE command spacing to
the same bank is four clocks and must also satisfy a minimum
analog time from the READ command. This time is called ^tRTP
(READ-to-PRECHARGE). ^tRTP starts AL cycles later than the
READ command. Examples for BL8 are shown in Figure 35
(page 77) and BC4 in Figure 36 (page 78). Following the
PRECHARGE command, a subsequent command to the same
bank cannot be issued until ^tRP is met. The PRECHARGE
command followed by another PRECHARGE command to
the same bank is allowed. However, the precharge period will
be determined by the last PRECHARGE command issued to
the bank.
If A10 is HIGH when a READ command is issued, the READ
with auto precharge function is engaged. The DRAM starts an
auto precharge operation on the rising edge, which is AL +
t_{RTP cycles after the READ command. DRAM support a} t_RAS
lockout feature Figure 38 (page 78). If ^tRAS (MIN) is not
satisfied at the edge, the starting point of the auto precharge
operation will be delayed until ^tRAS (MIN) is satisfied. If ^tRTP
(MIN) is not satisfied at the edge, the starting point of the auto
precharge operation is delayed until ^tRTP (MIN) is satisfied. In
case the internal precharge is pushed out by ^tRTP, ^tRP starts
at the point at which the internal precharge happens (not at the
next rising clock edge after this event). The time from READ
with auto precharge to the next ACTIVATE command to the
same bank is AL + (^tRTP + ^tRP)*, where * means rounded up
to the next integer. In any event, internal precharge does not
start earlier than four clocks after the last 8n-bit prefetch.
1Gb SDRAM-DDR3
MYX4DDR364M16JT*
*Advanced information. Subject to change without notice.
MYX4DDR364M16JT*
Revision 1.5 - 11/19/15
74
Form #: CSI-D-685 Document 007