MYX4DDR364M16JT Datasheet, PDF (1/128 Pages) Micross Components – 8n-bit prefetch architecture

1Gb SDRAM-DDR3
MYX4DDR364M16JT*
*Advanced information. Subject to change without notice.
1Gbit - 64M x 16 DDR3 SDRAM
Features
• Tin-lead ball metallurgy
• V_DD = V_DDQ = +1.35V (1.283V to 1.45V)
• Backward compatible to V_DD = V_DDQ = 1.5V -+0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data,
strobe, and mask signals
• Programmable CAS READ latency (CL)
• Programmable CAS additive latency (AL)
• Programmable CAS WRITE latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via
the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T_C of -40°C to 105°C
• 64ms, 8192-cycle refresh at -40°C to 85°C
• 32ms, at 85°C to 105°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
OptionsCode
• Configuration:
• 64 Meg x 16
64M16
• FBGA package (Sn63 / Pb37)
• 96-ball FBGA (8mm x 14mm)
TW
• Timing - cycle time
• 1.07ns @ CL = 13 (DDR3-1866)
-107
• Operating temperature
• Industrial (-40°C ≤ T_C ≤ +95°C)
IT
• Enhanced (-40°C ≤ T_C ≤ +105°C)
ET
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target ^tRCD-^tRP-CL ^tRCD (ns) ^tRP (ns) CL (ns)
-107
1866
13-13-13
13.91
Table 2: Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
Page Size
64 Meg x 16
8 Meg x 16 x 8 banks
8K
8K (A[12:0])
8 (BA[2:0])
1K (A[9:0])
2KB
MYX4DDR364M16JT*
Revision 1.5 - 11/19/15
1
Form #: CSI-D-685 Document 007