MYX4DDR364M16JT Datasheet, PDF (100/128 Pages) Micross Components – 8n-bit prefetch architecture

t_IS
CKE
IH
t_IS
t_PD
t_XP
Enter power-down
mode
Exit power-down
mode
1Gb SDRAM-DDR3
MYX4DDR364M16JT* Indicates break
in time scale
Don’t Care
*Advanced information. Subject to change without notice.
Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
Figure 60: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
T0
T1
T2
T3
T4
Ta
Ta1
Tb
CK#
CK
t_CK
t_CH
t_CL
Command
PRE
NOP
NOP
NOP
NOP
Valid¹
Valid²
t_CPDED
t_{CKE (MIN)}
t_IS
CKE
t_IH
t_IS
t_XP
t_XPDLL
t_PD
Notes:
Enter power-down
mode
Exit power-down
mode
Indicates break
in time scale
Don’t Care
1. Any valid command not requiring a locked DLL.
2.
Any
valid
command
re^Nq^ou^tir^ein^sg^:
a ¹lo^.ck^Aeⁿd^yD^vL^aL^l.^id
2. Any valid
command
command
not requiring a locked DLL.
requiring a locked DLL. ^1Gb:
x4,
x8,
x16
DDR3
SDRAM
Power-Down Mode
Figure 61: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
T0
T1
Ta0
CK#
CK
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Command
READ/
RDAP
NOP
NOP
Ta1
NOP
CKE
Address Valid
DQS, DQS#
RL = AL + CL
DQ BL8
DQ BC4
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
Ta11
Ta12
186
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2006 Micron Technology, Inc. All rights reserved.
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_IS t_CPDED
t_PD
DI DI DI DI DI DI DI DI
n n + 1 n + 2 n + 3 n + 4 n+ 5 n + 6 n + 7
DI DI DI DI
n n+1 n+2 n+3
t_RDPDEN
Power-down or
self refresh entry
Indicates break
in time scale
Transitioning Data
Don’t Care
Figure 101: Power-Down Entry After WRITE
MYX4DDR364M16JT*
RevisionC1K#.5 - 1^T1⁰ /19/15 ^T1
Ta0
Ta1
Ta2
Ta3
Ta4 ₁₀₀ Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
Tb3
Tb4
CK
Command WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Form #: CSI-D-685 Document 007