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| MYX4DDR364M16JT Datasheet, PDF (4/128 Pages) Micross Components – 8n-bit prefetch architecture | |||
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Figure 8: 96-Ball FBGA â x16 (Top View)
Figure 2: 96-Ball
FBGA â x16 (Top
View)
1234
A
VDDQ DQ13 DQ15
B
VSSQ
VDD
VSS
C
VDDQ DQ11 DQ9
D
VSSQ
VDDQ UDM
E
VSS
VSSQ
DQ0
F
VDDQ DQ2 LDQS
G
VSSQ
DQ6 LDQS#
H
VREFDQ VDDQ
DQ4
J
NC
VSS
RAS#
K
ODT
VDD
CAS#
L
NC
CS#
WE#
M
VSS
BA0
BA2
N
VDD
A3
A0
P
VSS
A5
A2
R
VDD
A7
A9
T
VSS RESET# NC
1Gb: x4, 1x8G,bx1S6DDRDAR3MS-DDRDARM3
Ball AssignmMenYtXs4aDnDd RD3es6c4rMipt1i6onJTs *
*Advanced information. Subject to change without notice.
56789
DQ12 VDDQ
VSS
UDQS# DQ14 VSSQ
UDQS DQ10 VDDQ
DQ8
VSSQ
VDD
LDM
VSSQ
VDDQ
DQ1
DQ3
VSSQ
VDD
VSS
VSSQ
DQ7
DQ5
VDDQ
CK
VSS
NC
CK#
VDD
CKE
A10/AP ZQ
NC
NC
VREFCA
VSS
A12/BC# BA1
VDD
A1
A4
VSS
A11
A6
VDD
NC
A8
VSS
Notes:
1. Ball descriptionNsolistteesd: in T1a.blBxe4a3lal(pndadegsexc85ri)paatrrieeoltnishsteeldissaatesmdâexi4.n, xT8aâbifleun5iq(upea; goethe2r3w)isaer,ex4lisatneddxa8saârex4th,exs8aâmief.unique; otherwise,
2. Acocnofimgumraatiosenpoanralyt.eNsFth/TeDcQ2o.Snf#iAEgaxupcaraopmtlmiioepnsml;etoaaDstsh7leaeps=xha8NrdaceFto,fiennNsefiFgst/uhTareDasteQcioloenScn#otf.anibNglyleuâFrfauaspnetlcipeotclinoitean;sb.alEteosxblaatemshthwpeleedxeeD4nf7Ncino=FenNosfrFiag,TNDuseFrQla/eSTtcD#iotQavniSbao#lMe.nRNflyuSF.na(NscpyFtpmi/olTiebnDso.QltsoSat#rheeadpxe4pfinlieeds
in Table 3).
to the x8 configuration onlyâselectable between NF or TDQS# via MRS (symbols are de-
fined in Table 5).
MYX4DDR364M16JT*
Revision 1.5 - 11/19/15
4
Form #: CSI-D-685 Document 007
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