MYX4DDR264M16HW Datasheet, PDF (41/51 Pages) –

1Gb DDR2 SDRAM
MYX4DDR264M16HW*
AC Characteristics
Parameter
DQ and DM input setup time to DQS
DQ and DM input hold time to DQS
DQ and DM input setup time to DQS
DQ and DM input hold time to DQS
DQ and DM input pulse width
Input setup time
Input hold time
Input setup time
Input hold time
Input pulse width
ACTIVATE-to- ACTIVATE delay, same bank
ACTIVATE-to-READ or WRITE delay
ACTIVATE-to-PRECHARGE delay
PRECHARGE period
PRECHARGE ALL period <1Gb
ACTIVATE-to-ACTIVATE delay different bank
4-bank activate period (≥1Gb)
Internal READ-to-PRECHARGE delay
CAS#-to-CAS# delay
Write recovery time
Write AP recovery + precharge time
Internal WRITE-to-READ delay
LOAD MODE cycle time
<1Gb
≥1Gb
REFRESH- to- ACTIVATE or to -REFRESH interval
Average periodic refresh (commercial)
Average periodic refresh (industrial)
*Advanced information. Subject to change without notice.
-25E
Symbol
Min
Max
Data In
t_DSb
50
–
t_DHb
125
–
t_DSa
250
–
t_DHa
250
–
t_DIPW
MIN = 0.35 × ^tCK; MAX = n/a
Command and Address
t_ISb
175
–
t_IHb
250
–
t_ISa
375
–
t_IHa
375
–
t_IPW
0.6
–
t_RC
55
–
t_RCD
12.5
–
t_RAS
40
70k
t_RP
12.5
–
t_RPA
12.5
–
t_RPA
15
–
t_RRD
10
–
t_FAW
45
–
t_RTP
7.5
–
t_CCD
2
–
t_WR
15
–
t_DAL
t_{WR +} t_RP
–
t_WTR
7.5
–
t_MRD
2
-
Refresh
t_RFC
127.5
–
t_REFI
–
7.8
t_REFIIT
–
3.9
Units Notes
ps
ps
26, 30, 31
ps
ps
t_{CK 18, 32}
ps
ps
31, 33
ps
ps
t_{CK 18, 32}
ns 18, 34, 51
ns
18
ns 18, 34, 35
ns
ns 18, 36
ns
ns 18, 37
ns 18, 38
ns 18, 37, 39
t_CK
18
ns 18, 37
ns
40
ns 18, 37
t_CK
18
–
μs 18, 41
μs
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
41
Form #: CSI-D-685 Document 005