MYX4DDR264M16HW Datasheet, PDF (1/51 Pages) –

1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
1Gb - 64M x 16 DDR2 SDRAM
Features
• Tin-lead ball metallurgy
• V_DD = 1.8V ±0.1V, V_DDQ = 1.8V ±0.1V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Duplicate output strobe
• DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 ^tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Industrial temperature (IT) option
• Supports JEDEC clock jitter specification
• AEC-Q100 (MIL version)
• PPAP submission (MIL version)
• 8D response time
Table 1: Key Timing Parameters
Speed
Grade
-25E
CL=3
400
Data Rate (MT/s)
CL=4
CL=5
CL=6
533
800
800
OptionsCode
• Configuration
ƒƒ 64 Meg x 16
(8 Meg x 16 x 8 banks)
64M16
• FBGA package (Sn63/Pb37)
BG
ƒƒ 84-ball FBGA (8mm x 12.5mm) Die Rev: H HR
ƒƒ 84-ball FBGA (8mm x 12.5mm) Die Rev :M NF
• Timing – cycle time
ƒƒ 2.5ns @ CL = 5 (DDR2-800)
-25E
• Operating temperature
ƒƒ Industrial (–40°C ≤ T_C ≤ +95°C;
IT
–40°C ≤ T_A ≤ +85°C)
ƒƒ Military (–55°C ≤ T_C ≤ +125°C)
XT
CL=7
n/a
t_{RC (ns)}
55
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
64 Meg x 16
8 Meg x 16 x 8 banks
8K
A[12:0] (8K)
BA[2:0] (8)
A[9:0] (1K)
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
1
Form #: CSI-D-685 Document 005