MYX4DDR264M16HW Datasheet, PDF (18/51 Pages) –

1Gb DDR2 SDRAM
MYX4DDR264M16HW*
*Advanced information. Subject to change without notice.
6
Extended Mode Register 2 (EMR2)
2Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 2 (EMR2)
The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently
Exte_an_{ll b}d_itse_id_{n E}M_MRo₂ d_aree_reR_see_rvg_edi_,s_et_xe_cer_pt2_for(E_E7M_{, w}R_hic2_h)_{is used in commercial or high-temperature operations, as}
shown in Figure 7. The_TE_hM_e R_ex2_teis_np_dr_eo_dgr_mam_om_deed_rev_gi_ia_steh_re₂LM_(EMco_Rm₂m_{) c}a_on_nd_ta_rond_lsw_fuill_nr_ce_tt_ia_oin_nsth_be_es_yt_onre_dd_ti_hnf_oo_sr_em_ca_oti_non_troun_llt_eil_dit_by
is programmed again othr eunmtilotdhe dreegviicsteelro.sCeusrpreonwtelyr. aRlel pbriotsgirnamEmMinRg2 tahreeEreMsRerwveilldn,oetxacleteprttfhoercEo7n,twenhtsicohf itsheused
memory array, provideⁱdⁿi^ct ^ois^mp^merf^eo^rr^cm^iae^ld^oc^ro^hrⁱr^ge^hct^-l^ty^e. ^{mperature operations, as shown in Figure 41. The EMR2 is pro-}
grammed via the LM command and will retain the stored information until it is pro-
Bit E7 (A7) must be p^gro^rag^mra^mm^eded^aga^asⁱⁿ“1^o”^r t^uoⁿp^tir^lo^tv^hid^ee^da^evfa^ics^ete^lr^or^se^ef^sre^ps^oh^wra^et^re^{. R}o^en^pI^rT^oga^rn^ad^mA^mTⁱdⁿe^gv^tic^he^es^Ei^Mf T^R_C ^wex^ilc^leⁿe^od^ts^alter
85°C.
the contents of the memory array, provided it is performed correctly.
Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT de-
EMR2 must be loaded_viw_ceh_sen_if a_Tll_Cb_ea_xn_ck_es_edar_se₈i₅d_°le_C.and no bursts are in progress, and the controller must wait the
specified time ^tMRD before initiating any subsequent operation. Violating either of these requirements could
result
in
an
unspecified^EcoMo_np^Rte_r2r_oa^mlt_lio_eurn^s._mt ^{buestlowaadiet dthwehspenecailfliebdantikmsear}_tMe ^iRdDle
and no bursts are in
before initiating any
progress, and the
subsequent opera-
tion. Violating either of these requirements could result in an unspecified operation.
Figure 7: EMR2 Definition
Figure 41: EMR2 Definition
BA21 BA1 BA0 An2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MRS 0 0 0 0 0 0 SRT 0 0 0 0 0 0 0
Extended mode
register (Ex)
E15 E14
Mode Register Set
00
Mode register (MR)
0 1 Extended mode register (EMR)
1 0 Extended mode register (EMR2)
1 1 Extended mode register (EMR3)
E7
SRT Enable
0 1X refresh rate (0°C to 85°C)
1 2X refresh rate (>85°C)
Notes:
Notes: 1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be pro-
grammed to “0.”
1. E16 (BA2) is only app₂li_.ca_Mb_ole_df_eor_bd_ite_sn_(Es_niti₎e_ws _i≥_t1_hG_cob_r,_rr_ee_ss_pe_or_nve_dd_inf_gor_adfu_dtu_rere_ssu_bs_ae_l,_lsa₍n_Ad_n)m_gu_rs_et_ab_tee_rp_thro_ag_nra_Em₁₂m₍e_Ad₁₂to_{) a}“_r0_e.”_re-
2. Mode bits (En) with corresesrpvoenddfinogr faudtdureesussbeaallnsd(Amnu) sgtrebaeteprrothgarnamEm12ed(At1o2“) 0a.r”e reserved for future use
and must be programmed to “0.”
MYX4DDR264M16HW*
Revision 1.4 - 03/29/2016
18
Form #: CSI-D-685 Document 005